static void setup_usb_phy(struct exynos_usb_phy *usb)
{
set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
if (cpu_is_exynos5())
exynos5_setup_usb_phy(usb);
else if (cpu_is_exynos4())
if (proid_is_exynos4412())
exynos4412_setup_usb_phy((struct exynos4412_usb_phy *)
usb);
}
/* Setup the EHCI host controller. */
static void setup_usb_phy(struct exynos_usb_phy *usb)
{
u32 hsic_ctrl;
set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
clrbits_le32(&usb->usbphyctrl0,
HOST_CTRL0_FSEL_MASK |
HOST_CTRL0_COMMONON_N |
/* HOST Phy setting */
HOST_CTRL0_PHYSWRST |
HOST_CTRL0_PHYSWRSTALL |
HOST_CTRL0_SIDDQ |
HOST_CTRL0_FORCESUSPEND |
HOST_CTRL0_FORCESLEEP);
setbits_le32(&usb->usbphyctrl0,
/* Setting up the ref freq */
(CLK_24MHZ << 16) |
/* HOST Phy setting */
HOST_CTRL0_LINKSWRST |
HOST_CTRL0_UTMISWRST);
udelay(10);
clrbits_le32(&usb->usbphyctrl0,
HOST_CTRL0_LINKSWRST |
HOST_CTRL0_UTMISWRST);
/* HSIC Phy Setting */
hsic_ctrl = (HSIC_CTRL_FORCESUSPEND |
HSIC_CTRL_FORCESLEEP |
HSIC_CTRL_SIDDQ);
clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
hsic_ctrl = (((HSIC_CTRL_REFCLKDIV_12 & HSIC_CTRL_REFCLKDIV_MASK)
<< HSIC_CTRL_REFCLKDIV_SHIFT)
| ((HSIC_CTRL_REFCLKSEL & HSIC_CTRL_REFCLKSEL_MASK)
<< HSIC_CTRL_REFCLKSEL_SHIFT)
| HSIC_CTRL_UTMISWRST);
setbits_le32(&usb->hsicphyctrl1, hsic_ctrl);
setbits_le32(&usb->hsicphyctrl2, hsic_ctrl);
udelay(10);
clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST |
HSIC_CTRL_UTMISWRST);
clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST |
HSIC_CTRL_UTMISWRST);
udelay(20);
/* EHCI Ctrl setting */
setbits_le32(&usb->ehcictrl,
EHCICTRL_ENAINCRXALIGN |
EHCICTRL_ENAINCR4 |
EHCICTRL_ENAINCR8 |
EHCICTRL_ENAINCR16);
}
