/* the fixed and variable MTTRs are power-up with random values, * clear them to MTRR_TYPE_UNCACHEABLE for safty. */ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) { /* Precondition: * The cache is not enabled in cr0 nor in MTRRdefType_MSR * entry32.inc ensures the cache is not enabled in cr0 */ msr_t msr; const unsigned long *msr_addr; /* Inialize all of the relevant msrs to 0 */ msr.lo = 0; msr.hi = 0; unsigned long msr_nr; for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) { wrmsr(msr_nr, msr); } #if defined(CONFIG_XIP_ROM_SIZE) /* enable write through caching so we can do execute in place * on the flash rom. * Determine address by calculating the XIP_ROM_SIZE sized area with * XIP_ROM_SIZE alignment that contains the global variable defined above; */ unsigned long f = (unsigned long)&addr_det & ~(CONFIG_XIP_ROM_SIZE - 1); set_var_mtrr(1, f, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif /* Set the default memory type and enable fixed and variable MTRRs */ /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; wrmsr(MTRRdefType_MSR, msr); }
static void cache_ramstage(void) { /* Enable caching for lower 1MB and ram stage using variable mtrr */ disable_cache(); set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); }
void cache_as_ram_new_stack (void) { void *resume_backup_memory = NULL; print_car_debug("Top about %08x ... Done\n", (uint32_t) &resume_backup_memory); print_car_debug("Disabling cache as ram now\n"); disable_cache_as_ram_bsp(); disable_cache(); /* Enable cached access to RAM in the range 1M to CONFIG_RAMTOP */ set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); if (acpi_is_wakeup_s3()) { resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); print_car_debug("Resume backup memory location: %p\n", resume_backup_memory); } prepare_ramstage_region(resume_backup_memory); set_sysinfo_in_ram(1); // So other core0 could start to train mem /*copy and execute ramstage */ copy_and_run(); /* We will not return */ print_car_debug("should not be here -\n"); }
static void enable_rom_caching(void) { msr_t msr; disable_cache(); set_var_mtrr(1, 0xffffffff - CACHE_ROM_SIZE + 1, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); enable_cache(); /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void enable_rom_caching(void) { msr_t msr; disable_cache(); /* Why only top 4MiB ? */ set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); enable_cache(); /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; wrmsr(MTRRdefType_MSR, msr); }
static void cache_bios_region(void) { int mtrr; uint32_t rom_size, alignment; mtrr = get_free_var_mtrr(); if (mtrr==-1) return; /* Only the IFD BIOS region is memory mapped (at top of 4G) */ rom_size = CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START; /* Round to power of two */ alignment = 1 << (log2_ceil(rom_size)); rom_size = ALIGN_UP(rom_size, alignment); set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT); }
asmlinkage void cache_as_ram_new_stack(void) { print_car_debug("Disabling cache as RAM now\n"); disable_cache_as_ram_real(0); // inline disable_cache(); /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); prepare_ramstage_region(acpi_is_wakeup_s3()); set_sysinfo_in_ram(1); // So other core0 could start to train mem /*copy and execute ramstage */ copy_and_run(); /* We will not return */ print_car_debug("should not be here -\n"); }