示例#1
0
int __init ralink_wdt_init_module(void)
{
	// initialize WDG timer (Timer1)
	setup_timer(&wdg_timer, on_refresh_wdg_timer, 0);

	set_wdg_timer_mode(TMR1CTL, WATCHDOG);
#if defined (CONFIG_RALINK_RT2880) || defined (CONFIG_RALINK_RT2883) || \
    defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883)
	/*
	 * System Clock = CPU Clock/2
	 * For user easy configuration, We assume the unit of watch dog timer is 1s, 
	 * so we need to calculate the TMR1LOAD value.
	 * Unit= 1/(SysClk/65536), 1 Sec = (SysClk)/65536
	 */
	set_wdg_timer_clock_prescale(TMR1CTL, SYS_CLK_DIV65536);
	wdg_load_value = CONFIG_RALINK_TIMER_WDG_REBOOT_DELAY * (get_surfboard_sysclk() / 65536);
#elif defined (CONFIG_RALINK_MT7621)
	set_wdg_timer_clock_prescale(1000); //1ms
	wdg_load_value = CONFIG_RALINK_TIMER_WDG_REBOOT_DELAY * 1000;
	sysRegWrite(TMR1LOAD, wdg_load_value);
#else  /* RT3352/RT5350/MT7620 */
	set_wdg_timer_clock_prescale(TMR1CTL, SYS_CLK_DIV65536);
	wdg_load_value = CONFIG_RALINK_TIMER_WDG_REBOOT_DELAY * (40000000 / 65536);
#endif

	on_refresh_wdg_timer(0);

	set_wdg_timer_ebl(TMR1CTL, 1);

	printk("Load Ralink WDG Timer Module\n");

	return 0;
}
示例#2
0
int32_t __init wdt_init_module(void)
{
    printk("Load Kernel WDG Timer Module\n");

    /* 
     * System Clock = CPU Clock/2
     * For user easy configuration, We assume the unit of watch dog timer is 1s, 
     * so we need to calculate the TMR1LOAD value.
     *
     * Unit= 1/(SysClk/65536), 1 Sec = (SysClk)/65536 
     *
     */

    // initialize WDG timer (Timer1)
    setup_wdg_timer(&wdg_timer, refresh_wdg_timer, 0);
    set_wdg_timer_mode(TMR1CTL,WATCHDOG);
    set_wdg_timer_clock_prescale(TMR1CTL,SYS_CLK_DIV65536);
    wdg_load_value = CONFIG_RALINK_WDG_TIMER * (get_surfboard_sysclk()/65536);

#if defined (CONFIG_RALINK_RT2880) || defined (CONFIG_RALINK_RT2883) || \
    defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3883)
    wdg_load_value =  CONFIG_RALINK_WDG_TIMER * (get_surfboard_sysclk()/65536);
#else
    wdg_load_value =  CONFIG_RALINK_WDG_TIMER * (40000000/65536); //fixed at 40Mhz
#endif

    refresh_wdg_timer(wdg_load_value);
    set_wdg_timer_ebl(TMR1CTL,1);

    return 0;
}