static void SA9602BPW(uint32 A, uint8 V) { setprg8r(EXPREGS[1],A,V&0x3F); if(MMC3_cmd&0x40) setprg8r(0,0x8000,~(1)); else setprg8r(0,0xc000,~(1)); setprg8r(0,0xe000,~(0)); }
static void Sync(void) { setprg2r(0,0xE000,0); setprg2r(0,0xE800,0); setprg2r(0,0xF000,0); setprg2r(0,0xF800,0); setprg8r(1,0x6000,3); setprg8r(1,0x8000,0); setprg8r(1,0xA000,1); setprg8r(1,0xC000,2); setchr8(chr & 1); setmirror(MI_V); }
static void FDSInit(void) { memset(FDSRegs,0,sizeof(FDSRegs)); writeskip=DiskPtr=DiskSeekIRQ=0; setmirror(1); setprg8r(0,0xe000,0); // BIOS setprg32r(1,0x6000,0); // 32KB RAM setchr8(0); // 8KB CHR RAM MapIRQHook=FDSFix; GameStateRestore=FDSStateRestore; SetReadHandler(0x4030,0x4030,FDSRead4030); SetReadHandler(0x4031,0x4031,FDSRead4031); SetReadHandler(0x4032,0x4032,FDSRead4032); SetReadHandler(0x4033,0x4033,FDSRead4033); SetWriteHandler(0x4020,0x4025,FDSWrite); SetWriteHandler(0x6000,0xdfff,FDSRAMWrite); SetReadHandler(0x6000,0xdfff,FDSRAMRead); SetReadHandler(0xE000,0xFFFF,FDSBIOSRead); IRQCount=IRQLatch=IRQa=0; FDSSoundReset(); InDisk=0; SelectDisk=0; }
static void Sync(void) { setchr8(0); setprg8r(0x10,0x6000,0); setprg32(0x8000,reg&0x1f); setmirror(((reg&0x20)>>5)^1); }
void GenMMC3Power(void) { if (UNIFchrrama) setchr8(0); SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite); SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite); SetReadHandler(0x8000, 0xFFFF, CartBR); A001B = A000B = 0; setmirror(1); if (mmc3opts & 1) { if (WRAMSIZE == 1024) { FCEU_CheatAddRAM(1, 0x7000, WRAM); SetReadHandler(0x7000, 0x7FFF, MAWRAMMMC6); SetWriteHandler(0x7000, 0x7FFF, MBWRAMMMC6); } else { FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM); SetWriteHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBW); SetReadHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBR); setprg8r(0x10, 0x6000, 0); } if (!(mmc3opts & 2)) FCEU_dwmemset(WRAM, 0, WRAMSIZE); } MMC3RegReset(); if (CHRRAM) FCEU_dwmemset(CHRRAM, 0, CHRRAMSIZE); }
void GenMMC3Power(void) { if (UNIFchrrama) setchr8(0); SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite); SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite); SetReadHandler(0x8000, 0xFFFF, CartBR); // KT-008 boards hack 2-in-1, TODO assign to new ines mapper, most dump of KT-boards on the net are mapper 4, so need database or goodnes fix support SetWriteHandler(0x5000,0x5FFF, KT008HackWrite); A001B = A000B = 0; setmirror(1); if (mmc3opts & 1) { if (WRAMSIZE == 1024) { FCEU_CheatAddRAM(1, 0x7000, WRAM); SetReadHandler(0x7000, 0x7FFF, MAWRAMMMC6); SetWriteHandler(0x7000, 0x7FFF, MBWRAMMMC6); } else { FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM); SetWriteHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBW); SetReadHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBR); setprg8r(0x10, 0x6000, 0); } if (!(mmc3opts & 2)) FCEU_dwmemset(WRAM, 0, WRAMSIZE); } MMC3RegReset(); if (CHRRAM) FCEU_dwmemset(CHRRAM, 0, CHRRAMSIZE); }
static void Sync(void) { uint8 i; setprg8r(0x10,0x6000,0); setprg8(0x8000,prg[0]); setprg8(0xa000,prg[1]); setprg8(0xc000,~1); setprg8(0xe000,~0); for(i=0; i<8; i++) { uint32 chr = chrlo[i]|(chrhi[i]<<8); if(chrlo[i]==0xc8) { vlock = 0; continue; } else if(chrlo[i]==0x88) { vlock = 1; continue; } if(((chrlo[i]==4)||(chrlo[i]==5))&&!vlock) setchr1r(0x10,i<<10,chr&1); else setchr1(i<<10,chr); } switch(mirr) { case 0: setmirror(MI_V); break; case 1: setmirror(MI_H); break; case 2: setmirror(MI_0); break; case 3: setmirror(MI_1); break; } }
static void Sync(void) { setprg4r(1,0x5000,1); setprg8r(1,0x6000,1); setprg32(0x8000,prg); setchr8(0); }
static void Sync(void) { setmirror(reg[0]); setprg8r(0x10,0x6000,0); setchr8(0); setprg32(0x8000,(reg[1]+reg[2])&0xf); }
static void Sync(void) { setchr8(0); setprg8r(0x10,0x6000,0); setprg32(0x8000,reg[1]>>1); setmirror((reg[0]&1)^1); }
void MDFN_VSUniPower(void) { coinon = 0; VSindex = 0; memset(WRAM, 0xFF, 8192); setprg8r(0x10, 0x6000, 0); }
static void Sync(void) { setprg8(0x6000, reg); setprg8(0x8000, ~3); setprg8(0xa000, ~2); setprg8r(0x10, 0xc000, 0); setprg8(0xe000, ~0); setchr8(0); }
static void M153Power(void) { BandaiSync(); setprg8r(0x10,0x6000,0); SetReadHandler(0x6000,0x7FFF,CartBR); SetWriteHandler(0x6000,0x7FFF,CartBW); SetReadHandler(0x8000,0xFFFF,CartBR); SetWriteHandler(0x8000,0xFFFF,BandaiWrite); }
static void UNLSC127Power(void) { Sync(); setprg8r(0x10, 0x6000, 0); setprg8(0xE000, ~0); SetReadHandler(0x6000, 0x7fff, CartBR); SetWriteHandler(0x6000, 0x7fff, CartBW); SetReadHandler(0x8000, 0xFFFF, CartBR); SetWriteHandler(0x8000, 0xFFFF, UNLSC127Write); }
static void Sync(void) { setprg2r(0x10, 0x0800, 0); setprg2r(0x10, 0x1000, 1); setprg2r(0x10, 0x1800, 2); setprg8r(0x10, 0x6000, 1); setprg16(0x8000, 0); setprg16(0xC000, ~0); setchr8(0); }
static void Sync(void) { setchr2(0x0000, chr_reg[0]); setchr2(0x0800, chr_reg[1]); setchr2(0x1000, chr_reg[2]); setchr2(0x1800, chr_reg[3]); setprg8r(0x10, 0x6000, 0); setprg16r((PRGptr[1]) ? kogame : 0, 0x8000, prg_reg); setprg16(0xC000, ~0); }
static void MMC5WRAM(uint32 A, uint32 V) { //printf("%02x\n",V); V=MMC5WRAMIndex[V&7]; if(V!=255) { setprg8r(0x10,A,V); MMC5MemIn[(A-0x6000)>>13]=1; }
static void SyncLH10(void) { setprg8(0x6000, ~1); setprg8(0x8000, reg[6]); setprg8(0xA000, reg[7]); setprg8r(0x10, 0xC000, 0); setprg8(0xE000, ~0); setchr8(0); setmirror(0); }
static void Sync(void) { setprg8r(0x10,0x6000,0); setprg8(0x8000,prg[0]); setprg8(0xA000,prg[1]); setprg8(0xC000,prg[2]); setprg8(0xE000,prg[3]); setchr8(chr); }
static void Power(CartInfo *info) { if(!info->battery) memset(WRAM, 0xFF, 8192); PRGBank32 = 0; CHRBanks[0] = 0; CHRBanks[1] = 1; setprg8r(0x10, 0x6000, 0); Sync(); }
void Mapper69_StateRestore(int version) { if(mapbyte1[1]&0x40) { if(mapbyte1[1]&0x80) // Select WRAM setprg8r(0x10,0x6000,0); } else setprg8(0x6000,mapbyte1[1]); }
static void Sync(void) { // setchr4(0x0000,(reg[0]&0x80) >> 7); // setchr4(0x1000,(reg[0]&0x80) >> 7); setchr8(0); setprg8r(0x10,0x6000,0); setprg16(0x8000,bs_tbl[reg[0]&0x7f]>>4); setprg16(0xc000,bs_tbl[reg[0]&0x7f]&0xf); setmirror(MI_V); }
static void Sync(void) { int i; setprg8r(0x10, 0x6000, 0); setprg8(0x8000, reg[0]); setprg8(0xA000, reg[1]); setprg8(0xC000, reg[2]); setprg8(0xE000, ~0); for (i = 0; i < 8; i++) setchr1(i << 10, chr[i]); setmirror(reg[3] ^ 1); }
static void M112Power(void) { bank=0; setprg16(0xC000,~0); setprg8r(0x10,0x6000,0); SetReadHandler(0x8000,0xFFFF,CartBR); SetWriteHandler(0x8000,0xFFFF,M112Write); SetWriteHandler(0x4020,0x5FFF,M112Write); SetReadHandler(0x6000,0x7FFF,CartBR); SetWriteHandler(0x6000,0x7FFF,CartBW); }
static void M15Power(void) { latchea=0x8000; latched=0; setchr8(0); setprg8r(0x10,0x6000,0); SetReadHandler(0x6000,0x7FFF,CartBR); SetWriteHandler(0x6000,0x7FFF,CartBW); SetWriteHandler(0x8000,0xFFFF,M15Write); SetReadHandler(0x8000,0xFFFF,CartBR); Sync(); }
static void Sync(void) { uint16 swap = ((mirr & 2) << 13); setmirror((mirr & 1) ^ 1); setprg8r(0x10, 0x6000, 0); setprg8(0x8000 ^ swap, preg[0]); setprg8(0xA000, preg[1]); setprg8(0xC000 ^ swap, ~1); setprg8(0xE000, ~0); uint8 i; for (i = 0; i < 8; i++) setchr1(i << 10, creg[i]); }
static void Sync(void) { uint32 i; for (i = 0; i < 8; i++) setchr1(i << 10, chrlo[i] | (chrhi[i] << 8)); setprg8r(0x10, 0x6000, 0); setprg16(0x8000, prg); setprg16(0xC000, ~0); if (mirrisused) setmirror(mirr ^ 1); else setmirror(MI_0); }
static void Sync(void) { setmirror((mode ^ 1) & 1); setprg8r(0x10, 0x6000, 0); setchr4(0x0000, lastnt); setchr4(0x1000, 1); if (mode & 4) setprg32(0x8000, prg & 7); else { setprg16(0x8000, prg & 0x0f); setprg16(0xC000, 0); } }
static void Sync(void) { setmirror(mirr); setprg8r(0x10,0x6000,0); setchr8(0); if(prgmode) setprg32(0x8000,prg&7); else { setprg16(0x8000,prg&0x0f); setprg16(0xC000,0); } }
static void Sync(void) { uint8 bank = (reg[2] & 3) << 3; setmirror((reg[0] & 1) ^ 1); setprg8r(0x10, 0x6000, 0); setchr8(0); if (reg[0] & 2) { setprg16(0x8000, (reg[1] & 7) | bank); setprg16(0xC000, ((~0) & 7) | bank); } else { setprg16(0x8000, (reg[1] & 6) | bank); setprg16(0xC000, (reg[1] & 6) | bank | 1); } }