static void extmoduleDsm2Start() { EXTERNAL_MODULE_ON(); setupPulsesDSM2(EXTERNAL_MODULE); GPIO_InitTypeDef GPIO_InitStructure; GPIO_PinAFConfig(EXTMODULE_GPIO, EXTMODULE_GPIO_PinSource, EXTMODULE_GPIO_AF); GPIO_InitStructure.GPIO_Pin = EXTMODULE_GPIO_PIN; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(EXTMODULE_GPIO, &GPIO_InitStructure); EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ; EXTMODULE_TIMER->ARR = 44000 ; // 22mS EXTMODULE_TIMER->CCR2 = 40000 ; // Update time EXTMODULE_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ; EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1 ; // O/P idle high EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0]; EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high EXTMODULE_TIMER->EGR = 1 ; // Restart EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match EXTMODULE_TIMER->DCR = 13 ; // DMA to CC1 // Enable the DMA channel here, DMA2 stream 2, channel 7 DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; DMA2_Stream2->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->DMAR); DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]); // DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // DMA2_Stream2->NDTR = 100 ; DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ; NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ; NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7); }
static void init_pa7_dsm2() { EXTERNAL_RF_ON(); // Timer8 setupPulsesDSM2(EXTERNAL_MODULE); RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ; // Enable portA clock #if defined(REV3) configure_pins( PIN_INTPPM_OUT, PIN_PERIPHERAL | PIN_PORTA | PIN_PER_1 | PIN_OS25 | PIN_PUSHPULL ) ; #else GPIO_InitTypeDef GPIO_InitStructure; RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIO_EXTPPM, ENABLE); GPIO_PinAFConfig(GPIO_EXTPPM, GPIO_PinSource_EXTPPM, GPIO_AF_TIM8); GPIO_InitStructure.GPIO_Pin = PIN_EXTPPM_OUT; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIO_EXTPPM, &GPIO_InitStructure); #endif RCC->APB2ENR |= RCC_APB2ENR_TIM8EN ; // Enable clock RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN ; // Enable DMA2 clock TIM8->CR1 &= ~TIM_CR1_CEN ; TIM8->ARR = 44000 ; // 22mS TIM8->CCR2 = 40000 ; // Update time TIM8->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 2000000 - 1 ; // 0.5uS from 30MHz #if defined(REV3) TIM8->CCER = TIM_CCER_CC1E | TIM_CCER_CC1P ; #else TIM8->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ; #endif TIM8->CR2 = TIM_CR2_OIS1 ; // O/P idle high TIM8->BDTR = TIM_BDTR_MOE ; // Enable outputs TIM8->CCR1 = dsm2Stream[0] ; TIM8->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high TIM8->EGR = 1 ; // Restart // TIM8->SR &= ~TIM_SR_UIF ; // Clear flag // TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag TIM8->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match TIM8->DCR = 13 ; // DMA to CC1 // TIM8->CR1 = TIM_CR1_OPM ; // Just run once // Enable the DMA channel here, DMA2 stream 2, channel 7 DMA2_Stream2->CR &= ~DMA_SxCR_EN ; // Disable DMA DMA2->LIFCR = DMA_LIFCR_CTCIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2 | DMA_LIFCR_CFEIF2 ; // Write ones to clear bits DMA2_Stream2->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 | DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ; DMA2_Stream2->PAR = CONVERT_PTR_UINT(&TIM8->DMAR); DMA2_Stream2->M0AR = CONVERT_PTR_UINT(&dsm2Stream[1]); // DMA2_Stream2->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // DMA2_Stream2->NDTR = 100 ; DMA2_Stream2->CR |= DMA_SxCR_EN ; // Enable DMA TIM8->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p TIM8->SR &= ~TIM_SR_CC2IF ; // Clear flag TIM8->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt TIM8->CR1 |= TIM_CR1_CEN ; NVIC_EnableIRQ(TIM8_CC_IRQn) ; NVIC_SetPriority(TIM8_CC_IRQn, 7); }