static int gfx2d_footswitch_disable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
uint32_t regval, rc = 0;
/* Return early if already disabled. */
regval = readl_relaxed(fs->gfs_ctl_reg);
if ((regval & ENABLE_BIT) == 0)
return 0;
/* Make sure required clocks are on at the correct rates. */
rc = setup_clocks(fs);
if (rc)
goto out;
/* Halt all bus ports in the power domain. */
if (fs->bus_port1) {
rc = msm_bus_axi_porthalt(fs->bus_port1);
if (rc) {
pr_err("%s: Port 1 halt failed.\n", __func__);
goto out;
}
}
/* Disable core clock. */
clk_disable(fs->core_clk);
/*
* Assert resets for all clocks in the clock domain so that
* outputs settle prior to clamping.
*/
if (fs->axi_clk)
clk_reset(fs->axi_clk, CLK_RESET_ASSERT);
clk_reset(fs->ahb_clk, CLK_RESET_ASSERT);
clk_reset(fs->core_clk, CLK_RESET_ASSERT);
/* Wait for synchronous resets to propagate. */
udelay(20);
/*
* Clamp the I/O ports of the core to ensure the values
* remain fixed while the core is collapsed.
*/
regval |= CLAMP_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
/* Collapse the power rail at the footswitch. */
regval &= ~ENABLE_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
/* Re-enable core clock. */
clk_enable(fs->core_clk);
/* Return clocks to their state before this function. */
restore_clocks(fs);
fs->is_enabled = false;
out:
return rc;
}
static int gfx2d_footswitch_disable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
struct fs_clk_data *clock;
uint32_t regval, rc = 0;
regval = readl_relaxed(fs->gfs_ctl_reg);
if ((regval & ENABLE_BIT) == 0)
return 0;
rc = setup_clocks(fs);
if (rc)
return rc;
clk_set_flags(fs->core_clk, CLKFLAG_NORETAIN);
if (fs->bus_port0) {
rc = msm_bus_axi_porthalt(fs->bus_port0);
if (rc) {
pr_err("%s port 0 halt failed.\n", fs->desc.name);
goto err;
}
}
clk_disable_unprepare(fs->core_clk);
for (clock = fs->clk_data; clock->clk; clock++)
;
for (clock--; clock >= fs->clk_data; clock--)
clk_reset(clock->clk, CLK_RESET_ASSERT);
udelay(5);
regval |= CLAMP_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
regval &= ~ENABLE_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
clk_prepare_enable(fs->core_clk);
restore_clocks(fs);
fs->is_enabled = false;
return 0;
err:
clk_set_flags(fs->core_clk, CLKFLAG_RETAIN);
restore_clocks(fs);
return rc;
}
void init(void) {
setup_flash();
setup_clocks();
setup_nvic();
systick_init(SYSTICK_RELOAD_VAL);
wirish::priv::board_setup_gpio();
setup_adcs();
setup_timers();
wirish::priv::board_setup_usb();
wirish::priv::series_init();
boardInit();
}
void
main(void) {
GPIO_OFF(E_NRST);
unstick_i2c();
GPIO_ON(E_NRST);
setup_clocks((int)info_get(boot_table, INFO_HSE_FREQ));
iwdg_start(4, 0xFFF);
watchdog_main = watchdog_net = 5;
ASSERT(xTaskCreate(main_thread, "main", MAIN_STACK_SIZE, NULL,
THREAD_PRIO_MAIN, &thread_main));
vTaskStartScheduler();
}
//Initialize functions for the board
//Starts up
void init(void) {
setup_flash();
setup_clocks();
setup_nvic();
systick_init(SYSTICK_RELOAD_VAL);
board_setup_gpio();
setup_timers();
board_setup_usb();
series_init();
disableDebugPorts();
}
void
setup(void) {
setup_clocks();
setup_pins();
// Initialize the USB device.
USB_Init();
// Turn on all low level interrupts.
PMIC.CTRL |= PMIC_LOLVLEN_bm;
// Turn on interrupts.
sei();
}
int board_late_init(void)
{
int ret = 0;
setup_ups();
if (!power_init())
setup_clocks();
ret = read_eeprom();
if (ret)
printf("Error %d reading EEPROM content!\n", ret);
eth_phy_reset();
show_eeprom();
read_board_id();
return ret;
}
/** \brief main loop to run tests.
*
* The tests being run are described in the documentation of this file.
*
* \return never returns, test loop runs ad infinitum. */
int main(void) {
uint8_t switch_mask = 0x00; // Input switches. Read hi when pressed
uint16_t result = 0;
SR_t shift_reg;
/* call all of the setup_* functions */
cli();
setup_clocks();
setup_LEDs();
setup_switches(switch_mask);
setup_SR(&shift_reg, &SR_PORT, &SR_SPI_MODULE, false);
setup_ADC(&ADC_PORT, &ADC_SPI_MODULE, ADC_CONVST_bm, ADC_EOC_bm,
ADC_callback);
setup_USART_BC();
sei();
set_channel(MPx, 15, &shift_reg);
set_channel(MPy, 15, &shift_reg);
/* signal debugging */
PORTD.DIRCLR |= PIN4_bm;
PORTD.PIN4CTRL = PORT_OPC_PULLDOWN_gc;
while (1)
{
if (ADC_ready(&adc)) {
// get a new conversion result
result = ADC_sample_once(&adc);
}
if (PORTD.IN & PIN4_bm) {
LED_PORT.OUT = 0xFF;
}
else {
LED_PORT.OUT = (uint8_t)(result >> 4);
printf("%u ", result);
}
}
}
static int gfx2d_footswitch_disable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
struct fs_clk_data *clock;
uint32_t regval, rc = 0;
/* Return early if already disabled. */
regval = readl_relaxed(fs->gfs_ctl_reg);
if ((regval & ENABLE_BIT) == 0)
return 0;
/* Make sure required clocks are on at the correct rates. */
rc = setup_clocks(fs);
if (rc)
return rc;
/* Allow core memory to collapse when its clock is gated. */
clk_set_flags(fs->core_clk, CLKFLAG_NORETAIN);
/* Halt all bus ports in the power domain. */
if (fs->bus_port0) {
rc = msm_bus_axi_porthalt(fs->bus_port0);
if (rc) {
pr_err("%s port 0 halt failed.\n", fs->desc.name);
goto err;
}
}
/* Disable core clock. */
clk_disable_unprepare(fs->core_clk);
/*
* Assert resets for all clocks in the clock domain so that
* outputs settle prior to clamping.
*/
for (clock = fs->clk_data; clock->clk; clock++)
; /* Do nothing */
for (clock--; clock >= fs->clk_data; clock--)
clk_reset(clock->clk, CLK_RESET_ASSERT);
/* Wait for synchronous resets to propagate. */
udelay(5);
/*
* Clamp the I/O ports of the core to ensure the values
* remain fixed while the core is collapsed.
*/
regval |= CLAMP_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
/* Collapse the power rail at the footswitch. */
regval &= ~ENABLE_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
/* Re-enable core clock. */
clk_prepare_enable(fs->core_clk);
/* Return clocks to their state before this function. */
restore_clocks(fs);
fs->is_enabled = false;
return 0;
err:
clk_set_flags(fs->core_clk, CLKFLAG_RETAIN);
restore_clocks(fs);
return rc;
}
static int gfx2d_footswitch_enable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
struct fs_clk_data *clock;
uint32_t regval, rc = 0;
mutex_lock(&claim_lock);
fs->is_claimed = true;
mutex_unlock(&claim_lock);
/* Return early if already enabled. */
regval = readl_relaxed(fs->gfs_ctl_reg);
if ((regval & (ENABLE_BIT | CLAMP_BIT)) == ENABLE_BIT)
return 0;
/* Make sure required clocks are on at the correct rates. */
rc = setup_clocks(fs);
if (rc)
return rc;
/* Un-halt all bus ports in the power domain. */
if (fs->bus_port0) {
rc = msm_bus_axi_portunhalt(fs->bus_port0);
if (rc) {
pr_err("%s port 0 unhalt failed.\n", fs->desc.name);
goto err;
}
}
/* Disable core clock. */
clk_disable_unprepare(fs->core_clk);
/*
* (Re-)Assert resets for all clocks in the clock domain, since
* footswitch_enable() is first called before footswitch_disable()
* and resets should be asserted before power is restored.
*/
for (clock = fs->clk_data; clock->clk; clock++)
; /* Do nothing */
for (clock--; clock >= fs->clk_data; clock--)
clk_reset(clock->clk, CLK_RESET_ASSERT);
/* Wait for synchronous resets to propagate. */
udelay(RESET_DELAY_US);
/* Enable the power rail at the footswitch. */
regval |= ENABLE_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
mb();
udelay(1);
/* Un-clamp the I/O ports. */
regval &= ~CLAMP_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
/* Deassert resets for all clocks in the power domain. */
for (clock = fs->clk_data; clock->clk; clock++)
clk_reset(clock->clk, CLK_RESET_DEASSERT);
udelay(RESET_DELAY_US);
/* Re-enable core clock. */
clk_prepare_enable(fs->core_clk);
/* Prevent core memory from collapsing when its clock is gated. */
clk_set_flags(fs->core_clk, CLKFLAG_RETAIN);
/* Return clocks to their state before this function. */
restore_clocks(fs);
fs->is_enabled = true;
return 0;
err:
restore_clocks(fs);
return rc;
}
static int footswitch_disable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
struct fs_clk_data *clock;
uint32_t regval, rc = 0;
/* Return early if already disabled. */
regval = readl_relaxed(fs->gfs_ctl_reg);
if ((regval & ENABLE_BIT) == 0)
return 0;
/* Make sure required clocks are on at the correct rates. */
rc = setup_clocks(fs);
if (rc)
return rc;
/* Allow core memory to collapse when its clock is gated. */
//if (fs->desc.id != FS_GFX3D_8064)
clk_set_flags(fs->core_clk, CLKFLAG_NORETAIN_MEM);
/* Halt all bus ports in the power domain. */
if (fs->bus_port0) {
rc = msm_bus_axi_porthalt(fs->bus_port0);
if (rc) {
pr_err("%s port 0 halt failed.\n", fs->desc.name);
goto err;
}
}
if (fs->bus_port1) {
rc = msm_bus_axi_porthalt(fs->bus_port1);
if (rc) {
pr_err("%s port 1 halt failed.\n", fs->desc.name);
goto err_port2_halt;
}
}
/*
* Assert resets for all clocks in the clock domain so that
* outputs settle prior to clamping.
*/
for (clock = fs->clk_data; clock->clk; clock++)
; /* Do nothing */
for (clock--; clock >= fs->clk_data; clock--)
clk_reset(clock->clk, CLK_RESET_ASSERT);
/* Wait for synchronous resets to propagate. */
udelay(fs->reset_delay_us);
/*
* Return clocks to their state before this function. For robustness
* if memory-retention across collapses is required, clocks should
* be disabled before asserting the clamps. Assuming clocks were off
* before entering footswitch_disable(), this will be true.
*/
restore_clocks(fs);
/*
* Clamp the I/O ports of the core to ensure the values
* remain fixed while the core is collapsed.
*/
regval |= CLAMP_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
/* Collapse the power rail at the footswitch. */
regval &= ~ENABLE_BIT;
#if defined(CONFIG_ARCH_MSM8930)
writel_relaxed(regval, fs->gfs_ctl_reg);
#else
if (fs->desc.id != FS_GFX3D)
writel_relaxed(regval, fs->gfs_ctl_reg);
#endif
fs->is_enabled = false;
return 0;
err_port2_halt:
msm_bus_axi_portunhalt(fs->bus_port0);
err:
clk_set_flags(fs->core_clk, CLKFLAG_RETAIN_MEM);
restore_clocks(fs);
return rc;
}
static int footswitch_enable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
struct fs_clk_data *clock;
uint32_t regval, rc = 0;
mutex_lock(&claim_lock);
fs->is_claimed = true;
mutex_unlock(&claim_lock);
/* Return early if already enabled. */
regval = readl_relaxed(fs->gfs_ctl_reg);
if ((regval & (ENABLE_BIT | CLAMP_BIT)) == ENABLE_BIT)
return 0;
/* Make sure required clocks are on at the correct rates. */
rc = setup_clocks(fs);
if (rc)
return rc;
/* Un-halt all bus ports in the power domain. */
if (fs->bus_port0) {
rc = msm_bus_axi_portunhalt(fs->bus_port0);
if (rc) {
pr_err("%s port 0 unhalt failed.\n", fs->desc.name);
goto err;
}
}
if (fs->bus_port1) {
rc = msm_bus_axi_portunhalt(fs->bus_port1);
if (rc) {
pr_err("%s port 1 unhalt failed.\n", fs->desc.name);
goto err_port2_halt;
}
}
/*
* (Re-)Assert resets for all clocks in the clock domain, since
* footswitch_enable() is first called before footswitch_disable()
* and resets should be asserted before power is restored.
*/
for (clock = fs->clk_data; clock->clk; clock++)
; /* Do nothing */
for (clock--; clock >= fs->clk_data; clock--)
clk_reset(clock->clk, CLK_RESET_ASSERT);
/* Wait for synchronous resets to propagate. */
udelay(fs->reset_delay_us);
/* Enable the power rail at the footswitch. */
regval |= ENABLE_BIT;
#if defined(CONFIG_ARCH_MSM8930)
writel_relaxed(regval, fs->gfs_ctl_reg);
#else
if (fs->desc.id != FS_GFX3D)
writel_relaxed(regval, fs->gfs_ctl_reg);
#endif
/* Wait for the rail to fully charge. */
mb();
udelay(1);
/* Un-clamp the I/O ports. */
regval &= ~CLAMP_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
/* Deassert resets for all clocks in the power domain. */
for (clock = fs->clk_data; clock->clk; clock++)
clk_reset(clock->clk, CLK_RESET_DEASSERT);
/* Toggle core reset again after first power-on (required for GFX3D). */
if (fs->desc.id == FS_GFX3D) {
clk_reset(fs->core_clk, CLK_RESET_ASSERT);
udelay(fs->reset_delay_us);
clk_reset(fs->core_clk, CLK_RESET_DEASSERT);
udelay(fs->reset_delay_us);
}
/* Prevent core memory from collapsing when its clock is gated. */
clk_set_flags(fs->core_clk, CLKFLAG_RETAIN_MEM);
/* Return clocks to their state before this function. */
restore_clocks(fs);
fs->is_enabled = true;
return 0;
err_port2_halt:
msm_bus_axi_porthalt(fs->bus_port0);
err:
restore_clocks(fs);
return rc;
}
static int gfx2d_footswitch_enable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
uint32_t regval, rc = 0;
mutex_lock(&claim_lock);
fs->is_claimed = true;
mutex_unlock(&claim_lock);
/* Return early if already enabled. */
regval = readl_relaxed(fs->gfs_ctl_reg);
if ((regval & (ENABLE_BIT | CLAMP_BIT)) == ENABLE_BIT)
return 0;
/* Make sure required clocks are on at the correct rates. */
rc = setup_clocks(fs);
if (rc)
goto out;
/* Un-halt all bus ports in the power domain. */
if (fs->bus_port1) {
rc = msm_bus_axi_portunhalt(fs->bus_port1);
if (rc) {
pr_err("%s: Port 1 unhalt failed.\n", __func__);
goto out;
}
}
/* Disable core clock. */
clk_disable(fs->core_clk);
/*
* (Re-)Assert resets for all clocks in the clock domain, since
* footswitch_enable() is first called before footswitch_disable()
* and resets should be asserted before power is restored.
*/
if (fs->axi_clk)
clk_reset(fs->axi_clk, CLK_RESET_ASSERT);
clk_reset(fs->ahb_clk, CLK_RESET_ASSERT);
clk_reset(fs->core_clk, CLK_RESET_ASSERT);
/* Wait for synchronous resets to propagate. */
udelay(20);
/* Enable the power rail at the footswitch. */
regval |= ENABLE_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
mb();
udelay(1);
/* Un-clamp the I/O ports. */
regval &= ~CLAMP_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
/* Deassert resets for all clocks in the power domain. */
if (fs->axi_clk)
clk_reset(fs->axi_clk, CLK_RESET_DEASSERT);
clk_reset(fs->ahb_clk, CLK_RESET_DEASSERT);
clk_reset(fs->core_clk, CLK_RESET_DEASSERT);
udelay(20);
/* Re-enable core clock. */
clk_enable(fs->core_clk);
/* Return clocks to their state before this function. */
restore_clocks(fs);
fs->is_enabled = true;
out:
return rc;
}
/** \brief main loop to run tests.
*
* The tests being run are described in the documentation of this file.
*
* \return never returns, test loop runs ad infinitum. */
int main(void) {
uint8_t switch_mask = PIN6_bm;
int16_t position = 0;
int16_t steps = 1000;
uint16_t accel = 100;
uint16_t decel = 100;
uint16_t speed = 800;
PS_t pressure_sensor;
LA_t LA_needle;
LA_t LA_ring;
command_t command;
uint16_t steps_left = 0;
/* call all of the setup_* functions */
cli();
setup_clocks();
setup_LEDs();
setup_switches(switch_mask);
setup_pressure_sensor(&pressure_sensor);
setup_USART_BC();
setup_linear_actuators(&LA_needle, &LA_ring);
sei();
/* shows the help menu */
show_help_message();
/* show the current state of the linear actuator */
show_motor_data(position, accel, decel, speed, steps);
while (1) {
switch(command = parse_command(&steps, &accel, &decel, &speed)) {
case STEP:
LA_move(&LA_needle, steps, accel, decel, speed);
LA_move(&LA_ring, steps, accel, decel, speed);
position += steps;
printf("\n\n");
break;
case MOVE:
LA_move(&LA_needle, steps, accel, decel, speed);
LA_move(&LA_ring, steps, accel, decel, speed);
position += steps;
printf("\n\n");
break;
case ACCEL:
case DECEL:
case SPEED:
printf("\n\n");
break;
case REPEAT:
LA_move(&LA_needle, steps, accel, decel, speed);
LA_move(&LA_ring, steps, accel, decel, speed);
position += steps;
printf("\n\n");
break;
case HELP:
show_help_message();
break;
case NONE:
break;
default:
show_help_message();
break;
}
if ((command != HELP) && (command != NONE)) {
while (LA_get_motor_state(&LA_needle) != SM_STOP) {
if (READ_SWITCHES & PIN6_bm) {
LA_brake(&LA_needle);
LA_brake(&LA_ring);
printf("motors parked\n");
}
if (steps > 0) {
steps_left = (int32_t)steps * SPR / LA_needle.pitch
- LA_needle.motor.speed_ramp.step_count;
}
else {
steps_left = -1 * (int32_t)steps * SPR / LA_needle.pitch
- LA_needle.motor.speed_ramp.step_count;
}
printf(" Running... Steps Left: %d\n", steps_left);
delay_ms(250);
}
printf(" Done with command\n");
show_motor_data(position, accel, decel, speed, steps);
}
}//end while (1)
}
static int gfx2d_footswitch_enable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
struct fs_clk_data *clock;
uint32_t regval, rc = 0;
mutex_lock(&claim_lock);
fs->is_claimed = true;
mutex_unlock(&claim_lock);
regval = readl_relaxed(fs->gfs_ctl_reg);
if ((regval & (ENABLE_BIT | CLAMP_BIT)) == ENABLE_BIT)
return 0;
rc = setup_clocks(fs);
if (rc)
return rc;
if (fs->bus_port0) {
rc = msm_bus_axi_portunhalt(fs->bus_port0);
if (rc) {
pr_err("%s port 0 unhalt failed.\n", fs->desc.name);
goto err;
}
}
clk_disable_unprepare(fs->core_clk);
for (clock = fs->clk_data; clock->clk; clock++)
;
for (clock--; clock >= fs->clk_data; clock--)
clk_reset(clock->clk, CLK_RESET_ASSERT);
udelay(RESET_DELAY_US);
regval |= ENABLE_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
mb();
udelay(1);
regval &= ~CLAMP_BIT;
writel_relaxed(regval, fs->gfs_ctl_reg);
for (clock = fs->clk_data; clock->clk; clock++)
clk_reset(clock->clk, CLK_RESET_DEASSERT);
udelay(RESET_DELAY_US);
clk_prepare_enable(fs->core_clk);
clk_set_flags(fs->core_clk, CLKFLAG_RETAIN);
restore_clocks(fs);
fs->is_enabled = true;
return 0;
err:
restore_clocks(fs);
return rc;
}
static int footswitch_enable(struct regulator_dev *rdev)
{
struct footswitch *fs = rdev_get_drvdata(rdev);
uint32_t regval, rc = 0;
mutex_lock(&claim_lock);
fs->is_claimed = 1;
mutex_unlock(&claim_lock);
/* Make sure required clocks are on at the correct rates. */
rc = setup_clocks(fs);
if (rc)
goto out;
/* (Re-)Assert resets for all clocks in the clock domain, since
* footswitch_enable() is first called before footswitch_disable()
* and resets should be asserted before power is restored. */
if (fs->axi_clk)
clk_reset(fs->axi_clk, CLK_RESET_ASSERT);
clk_reset(fs->ahb_clk, CLK_RESET_ASSERT);
clk_reset(fs->core_clk, CLK_RESET_ASSERT);
/* Wait for synchronous resets to propagate. */
udelay(RESET_DELAY_US);
/* Un-halt all bus ports in the power domain. */
if (fs->bus_port1) {
rc = msm_bus_axi_portunhalt(fs->bus_port1);
if (rc) {
pr_err("%s: Port 1 unhalt failed.\n", __func__);
goto out;
}
}
if (fs->bus_port2) {
rc = msm_bus_axi_portunhalt(fs->bus_port2);
if (rc) {
pr_err("%s: Port 2 unhalt failed.\n", __func__);
goto out;
}
}
/* Enable the power rail at the footswitch. */
regval = readl(fs->gfs_ctl_reg);
regval |= ENABLE_BIT;
writel(regval, fs->gfs_ctl_reg);
/* Wait 2us for the rail to fully charge. */
udelay(2);
/* Deassert resets for all clocks in the power domain. */
clk_reset(fs->core_clk, CLK_RESET_DEASSERT);
clk_reset(fs->ahb_clk, CLK_RESET_DEASSERT);
if (fs->axi_clk)
clk_reset(fs->axi_clk, CLK_RESET_DEASSERT);
/* Toggle core reset now that power is on (required for some cores). */
clk_reset(fs->core_clk, CLK_RESET_ASSERT);
udelay(RESET_DELAY_US);
clk_reset(fs->core_clk, CLK_RESET_DEASSERT);
udelay(RESET_DELAY_US);
/* Un-clamp the I/O ports. */
regval &= ~CLAMP_BIT;
writel(regval, fs->gfs_ctl_reg);
/* Wait for the clamps to clear and signals to settle. */
udelay(5);
/* Return clocks to their state before this function. */
restore_clocks(fs);
fs->is_enabled = 1;
out:
return rc;
}