int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc); setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3); #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif #ifdef CONFIG_TDX_CMD_IMX_MFGR (void) pmic_init(); #endif #ifdef CONFIG_SATA setup_sata(); #endif setup_iomux_gpio(); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_gpio(); setup_display(); return 0; }
int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_gpio(); gpio_direction_output(SOFT_RESET_GPIO, 1); gpio_direction_output(SD2_DRIVER_ENABLE, 1); setup_display(); set_gpr_register(); return 0; }
void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ arch_cpu_init(); ccgr_init(); gpr_init(); /* setup GP timer */ timer_init(); setup_iomux_boardid(); setup_iomux_gpio(); setup_iomux_enet(); setup_iomux_sd(); setup_iomux_spi(); setup_iomux_uart(); setup_iomux_usb(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* Start the DDR DRAM */ if (is_mx6dq()) mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs, &dhcom6dq_grp_ioregs); else mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs, &dhcom6sdl_grp_ioregs); mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* load/boot image from boot device */ board_init_r(NULL, 0); }
static void spl_dram_init(int width, int size_mb, int board_model) { struct mx6_ddr3_cfg *mem = NULL; struct mx6_mmdc_calibration *calib = NULL; struct mx6_ddr_sysinfo sysinfo = { /* width of data bus:0=16,1=32,2=64 */ .dsize = width/32, /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 32Gb per CS */ /* single chip select */ .ncs = 1, .cs1_mirror = 0, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ #ifdef RTT_NOM_120OHM .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ #else .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ #endif .walat = 1, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .pd_fast_exit = 1, /* enable precharge power-down fast exit */ .ddr_type = DDR_TYPE_DDR3, }; /* * MMDC Calibration requires the following data: * mx6_mmdc_calibration - board-specific calibration (routing delays) * these calibration values depend on board routing, SoC, and DDR * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) * mx6_ddr_cfg - chip specific timing/layout details */ if (width == 16 && size_mb == 128) { mem = &mt41k64m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) ; else calib = &mx6sdl_64x16_mmdc_calib; debug("1gB density\n"); } else if (width == 16 && size_mb == 256) { /* 1x 2Gb density chip - same calib as 2x 2Gb */ mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_128x32_mmdc_calib; else calib = &mx6sdl_128x32_mmdc_calib; debug("2gB density\n"); } else if (width == 16 && size_mb == 512) { mem = &mt41k256m16ha_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_256x16_mmdc_calib; else calib = &mx6sdl_256x16_mmdc_calib; debug("4gB density\n"); } else if (width == 32 && size_mb == 256) { /* Same calib as width==16, size==128 */ mem = &mt41k64m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) ; else calib = &mx6sdl_64x16_mmdc_calib; debug("1gB density\n"); } else if (width == 32 && size_mb == 512) { mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_128x32_mmdc_calib; else calib = &mx6sdl_128x32_mmdc_calib; debug("2gB density\n"); } else if (width == 32 && size_mb == 1024) { mem = &mt41k256m16ha_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_256x32_mmdc_calib; else calib = &mx6sdl_256x32_mmdc_calib; debug("4gB density\n"); } else if (width == 64 && size_mb == 512) { mem = &mt41k64m16jt_125; debug("1gB density\n"); } else if (width == 64 && size_mb == 1024) { mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_128x64_mmdc_calib; else calib = &mx6sdl_128x64_mmdc_calib; debug("2gB density\n"); } else if (width == 64 && size_mb == 2048) { mem = &mt41k256m16ha_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_256x64_mmdc_calib; debug("4gB density\n"); } if (!(mem && calib)) { puts("Error: Invalid Calibration/Board Configuration\n"); printf("MEM : %s\n", mem ? "OKAY" : "NULL"); printf("CALIB : %s\n", calib ? "OKAY" : "NULL"); printf("CPUTYPE: %s\n", is_cpu_type(MXC_CPU_MX6Q) ? "IMX6Q" : "IMX6DL"); printf("SIZE_MB: %d\n", size_mb); printf("WIDTH : %d\n", width); hang(); } if (is_cpu_type(MXC_CPU_MX6Q)) mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); else mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&sysinfo, calib, mem); } static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; writel(0x00C03F3F, &ccm->CCGR0); writel(0x0030FC03, &ccm->CCGR1); writel(0x0FFFC000, &ccm->CCGR2); writel(0x3FF00000, &ccm->CCGR3); writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ writel(0x0F0000C3, &ccm->CCGR5); writel(0x000003FF, &ccm->CCGR6); } static void gpr_init(void) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; /* enable AXI cache for VDOA/VPU/IPU */ writel(0xF00000CF, &iomux->gpr[4]); /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ writel(0x007F007F, &iomux->gpr[6]); writel(0x007F007F, &iomux->gpr[7]); } /* * called from C runtime startup code (arch/arm/lib/crt0.S:_main) * - we have a stack and a place to store GD, both in SRAM * - no variable global data is available */ void board_init_f(ulong dummy) { struct ventana_board_info ventana_info; int board_model; /* setup clock gating */ ccgr_init(); /* setup AIPS and disable watchdog */ arch_cpu_init(); /* setup AXI */ gpr_init(); /* iomux and setup of i2c */ setup_iomux_uart(); setup_ventana_i2c(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); /* read/validate EEPROM info to determine board model and SDRAM cfg */ board_model = read_eeprom(CONFIG_I2C_GSC, &ventana_info); /* configure model-specific gpio */ setup_iomux_gpio(board_model, &ventana_info); /* provide some some default: 32bit 128MB */ if (GW_UNKNOWN == board_model) hang(); /* configure MMDC for SDRAM width/size and per-model calibration */ spl_dram_init(8 << ventana_info.sdram_width, 16 << ventana_info.sdram_size, board_model); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); /* disable boot watchdog */ gsc_boot_wd_disable(); } /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ /* its our chance to print info about boot device */ void spl_board_init(void) { /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */ u32 boot_device = spl_boot_device(); switch (boot_device) { case BOOT_DEVICE_MMC1: puts("Booting from MMC\n"); break; case BOOT_DEVICE_NAND: puts("Booting from NAND\n"); break; case BOOT_DEVICE_SATA: puts("Booting from SATA\n"); break; default: puts("Unknown boot device\n"); } /* PMIC init */ setup_pmic(); }