void __init arch_init_irq(void)
{
int i;
unsigned long cp0_status;
au1xxx_irq_map_t *imp;
extern au1xxx_irq_map_t au1xxx_irq_map[];
extern au1xxx_irq_map_t au1xxx_ic0_map[];
extern int au1xxx_nr_irqs;
extern int au1xxx_ic0_nr_irqs;
cp0_status = read_c0_status();
set_except_vector(0, au1000_IRQ);
/* Initialize interrupt controllers to a safe state.
*/
au_writel(0xffffffff, IC0_CFG0CLR);
au_writel(0xffffffff, IC0_CFG1CLR);
au_writel(0xffffffff, IC0_CFG2CLR);
au_writel(0xffffffff, IC0_MASKCLR);
au_writel(0xffffffff, IC0_ASSIGNSET);
au_writel(0xffffffff, IC0_WAKECLR);
au_writel(0xffffffff, IC0_SRCSET);
au_writel(0xffffffff, IC0_FALLINGCLR);
au_writel(0xffffffff, IC0_RISINGCLR);
au_writel(0x00000000, IC0_TESTBIT);
au_writel(0xffffffff, IC1_CFG0CLR);
au_writel(0xffffffff, IC1_CFG1CLR);
au_writel(0xffffffff, IC1_CFG2CLR);
au_writel(0xffffffff, IC1_MASKCLR);
au_writel(0xffffffff, IC1_ASSIGNSET);
au_writel(0xffffffff, IC1_WAKECLR);
au_writel(0xffffffff, IC1_SRCSET);
au_writel(0xffffffff, IC1_FALLINGCLR);
au_writel(0xffffffff, IC1_RISINGCLR);
au_writel(0x00000000, IC1_TESTBIT);
/* Initialize IC0, which is fixed per processor.
*/
imp = au1xxx_ic0_map;
for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
imp++;
}
/* Now set up the irq mapping for the board.
*/
imp = au1xxx_irq_map;
for (i=0; i<au1xxx_nr_irqs; i++) {
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
imp++;
}
set_c0_status(ALLINTS);
/* Board specific IRQ initialization.
*/
if (board_init_irq)
(*board_init_irq)();
}
void __init init_IRQ(void)
{
int i;
unsigned long cp0_status;
cp0_status = read_32bit_cp0_register(CP0_STATUS);
memset(irq_desc, 0, sizeof(irq_desc));
set_except_vector(0, au1000_IRQ);
init_generic_irq();
/*
* Setup high priority interrupts on int_request0; low priority on
* int_request1
*/
for (i = 0; i <= NR_IRQS; i++) {
switch (i) {
case AU1000_MAC0_DMA_INT:
case AU1000_MAC1_DMA_INT:
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
default: /* active high, level interrupt */
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 1);
irq_desc[i].handler = &level_irq_type;
break;
}
}
set_cp0_status(ALLINTS);
#ifdef CONFIG_REMOTE_DEBUG
/* If local serial I/O used for debug port, enter kgdb at once */
puts("Waiting for kgdb to connect...");
set_debug_traps();
breakpoint();
#endif
}
void __init init_IRQ(void)
{
int i;
unsigned long cp0_status;
au1xxx_irq_map_t *imp;
extern au1xxx_irq_map_t au1xxx_irq_map[];
extern int au1xxx_nr_irqs;
cp0_status = read_c0_status();
memset(irq_desc, 0, sizeof(irq_desc));
set_except_vector(0, au1000_IRQ);
init_generic_irq();
for (i = 0; i <= AU1000_MAX_INTR; i++) {
/* default is active high, level interrupt */
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
}
/* Now set up the irq mapping for the board.
*/
imp = au1xxx_irq_map;
for (i=0; i<au1xxx_nr_irqs; i++) {
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
switch (imp->im_type) {
case INTC_INT_HIGH_LEVEL:
irq_desc[imp->im_irq].handler = &level_irq_type;
break;
case INTC_INT_LOW_LEVEL:
irq_desc[imp->im_irq].handler = &level_irq_type;
break;
case INTC_INT_RISE_EDGE:
irq_desc[imp->im_irq].handler = &rise_edge_irq_type;
break;
case INTC_INT_FALL_EDGE:
irq_desc[imp->im_irq].handler = &fall_edge_irq_type;
break;
case INTC_INT_RISE_AND_FALL_EDGE:
irq_desc[imp->im_irq].handler = &either_edge_irq_type;
break;
default:
panic("Unknown au1xxx irq map");
break;
}
imp++;
}
set_c0_status(ALLINTS);
/* Board specific IRQ initialization.
*/
if (board_init_irq)
(*board_init_irq)();
#ifdef CONFIG_KGDB
/* If local serial I/O used for debug port, enter kgdb at once */
puts("Waiting for kgdb to connect...");
set_debug_traps();
breakpoint();
#endif
}
void __init init_IRQ(void)
{
int i;
unsigned long cp0_status;
extern char except_vec0_au1000;
cp0_status = read_32bit_cp0_register(CP0_STATUS);
memset(irq_desc, 0, sizeof(irq_desc));
set_except_vector(0, au1000_IRQ);
init_generic_irq();
for (i = 0; i <= AU1000_MAX_INTR; i++) {
switch (i) {
case AU1000_UART0_INT:
case AU1000_UART3_INT:
#ifdef CONFIG_MIPS_PB1000
case AU1000_UART1_INT:
case AU1000_UART2_INT:
case AU1000_SSI0_INT:
case AU1000_SSI1_INT:
#endif
#ifdef CONFIG_MIPS_PB1100
case AU1000_UART1_INT:
case AU1000_SSI0_INT:
case AU1000_SSI1_INT:
#endif
case AU1000_DMA_INT_BASE:
case AU1000_DMA_INT_BASE+1:
case AU1000_DMA_INT_BASE+2:
case AU1000_DMA_INT_BASE+3:
case AU1000_DMA_INT_BASE+4:
case AU1000_DMA_INT_BASE+5:
case AU1000_DMA_INT_BASE+6:
case AU1000_DMA_INT_BASE+7:
case AU1000_IRDA_TX_INT:
case AU1000_IRDA_RX_INT:
case AU1000_MAC0_DMA_INT:
#ifdef CONFIG_MIPS_PB1000
case AU1000_MAC1_DMA_INT:
#endif
#ifdef CONFIG_MIPS_PB1500
case AU1000_MAC1_DMA_INT:
#endif
case AU1500_GPIO_204:
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
#ifdef CONFIG_MIPS_PB1000
case AU1000_GPIO_15:
#endif
case AU1000_USB_HOST_INT:
#ifdef CONFIG_MIPS_PB1500
case AU1000_PCI_INTA:
case AU1000_PCI_INTB:
case AU1000_PCI_INTC:
case AU1000_PCI_INTD:
case AU1500_GPIO_201:
case AU1500_GPIO_202:
case AU1500_GPIO_203:
case AU1500_GPIO_205:
case AU1500_GPIO_207:
#endif
#ifdef CONFIG_MIPS_PB1100
case AU1000_GPIO_9: // PCMCIA Card Fully_Interted#
case AU1000_GPIO_10: // PCMCIA_STSCHG#
case AU1000_GPIO_11: // PCMCIA_IRQ#
case AU1000_GPIO_13: // DC_IRQ#
case AU1000_GPIO_23: // 2-wire SCL
#endif
setup_local_irq(i, INTC_INT_LOW_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
case AU1000_ACSYNC_INT:
case AU1000_AC97C_INT:
case AU1000_TOY_INT:
case AU1000_TOY_MATCH0_INT:
case AU1000_TOY_MATCH1_INT:
case AU1000_USB_DEV_SUS_INT:
case AU1000_USB_DEV_REQ_INT:
case AU1000_RTC_INT:
case AU1000_RTC_MATCH0_INT:
case AU1000_RTC_MATCH1_INT:
case AU1000_RTC_MATCH2_INT:
setup_local_irq(i, INTC_INT_RISE_EDGE, 0);
irq_desc[i].handler = &rise_edge_irq_type;
break;
// Careful if you change match 2 request!
// The interrupt handler is called directly
// from the low level dispatch code.
case AU1000_TOY_MATCH2_INT:
setup_local_irq(i, INTC_INT_RISE_EDGE, 1);
irq_desc[i].handler = &rise_edge_irq_type;
break;
default: /* active high, level interrupt */
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
}
}
set_cp0_status(ALLINTS);
#ifdef CONFIG_REMOTE_DEBUG
/* If local serial I/O used for debug port, enter kgdb at once */
puts("Waiting for kgdb to connect...");
set_debug_traps();
breakpoint();
#endif
}
void __init init_IRQ(void)
{
int i;
unsigned long cp0_status;
au1xxx_irq_map_t *imp;
extern au1xxx_irq_map_t au1xxx_irq_map[];
extern au1xxx_irq_map_t au1xxx_ic0_map[];
extern int au1xxx_nr_irqs;
extern int au1xxx_ic0_nr_irqs;
cp0_status = read_c0_status();
memset(irq_desc, 0, sizeof(irq_desc));
set_except_vector(0, au1000_IRQ);
init_generic_irq();
/* Initialize interrupt controllers to a safe state.
*/
au_writel(0xffffffff, IC0_CFG0CLR);
au_writel(0xffffffff, IC0_CFG1CLR);
au_writel(0xffffffff, IC0_CFG2CLR);
au_writel(0xffffffff, IC0_MASKCLR);
au_writel(0xffffffff, IC0_ASSIGNSET);
au_writel(0xffffffff, IC0_WAKECLR);
au_writel(0xffffffff, IC0_SRCSET);
au_writel(0xffffffff, IC0_FALLINGCLR);
au_writel(0xffffffff, IC0_RISINGCLR);
au_writel(0x00000000, IC0_TESTBIT);
au_writel(0xffffffff, IC1_CFG0CLR);
au_writel(0xffffffff, IC1_CFG1CLR);
au_writel(0xffffffff, IC1_CFG2CLR);
au_writel(0xffffffff, IC1_MASKCLR);
au_writel(0xffffffff, IC1_ASSIGNSET);
au_writel(0xffffffff, IC1_WAKECLR);
au_writel(0xffffffff, IC1_SRCSET);
au_writel(0xffffffff, IC1_FALLINGCLR);
au_writel(0xffffffff, IC1_RISINGCLR);
au_writel(0x00000000, IC1_TESTBIT);
/* Initialize IC0, which is fixed per processor.
*/
imp = au1xxx_ic0_map;
for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
imp++;
}
/* Now set up the irq mapping for the board.
*/
imp = au1xxx_irq_map;
for (i=0; i<au1xxx_nr_irqs; i++) {
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
imp++;
}
set_c0_status(ALLINTS);
/* Board specific IRQ initialization.
*/
if (board_init_irq)
(*board_init_irq)();
#ifdef CONFIG_KGDB
/* If local serial I/O used for debug port, enter kgdb at once */
puts("Waiting for kgdb to connect...");
set_debug_traps();
breakpoint();
#endif
}
void __init arch_init_irq(void)
{
int i;
struct au1xxx_irqmap *imp;
extern struct au1xxx_irqmap au1xxx_irq_map[];
extern struct au1xxx_irqmap au1xxx_ic0_map[];
extern int au1xxx_nr_irqs;
extern int au1xxx_ic0_nr_irqs;
/*
* Initialize interrupt controllers to a safe state.
*/
au_writel(0xffffffff, IC0_CFG0CLR);
au_writel(0xffffffff, IC0_CFG1CLR);
au_writel(0xffffffff, IC0_CFG2CLR);
au_writel(0xffffffff, IC0_MASKCLR);
au_writel(0xffffffff, IC0_ASSIGNSET);
au_writel(0xffffffff, IC0_WAKECLR);
au_writel(0xffffffff, IC0_SRCSET);
au_writel(0xffffffff, IC0_FALLINGCLR);
au_writel(0xffffffff, IC0_RISINGCLR);
au_writel(0x00000000, IC0_TESTBIT);
au_writel(0xffffffff, IC1_CFG0CLR);
au_writel(0xffffffff, IC1_CFG1CLR);
au_writel(0xffffffff, IC1_CFG2CLR);
au_writel(0xffffffff, IC1_MASKCLR);
au_writel(0xffffffff, IC1_ASSIGNSET);
au_writel(0xffffffff, IC1_WAKECLR);
au_writel(0xffffffff, IC1_SRCSET);
au_writel(0xffffffff, IC1_FALLINGCLR);
au_writel(0xffffffff, IC1_RISINGCLR);
au_writel(0x00000000, IC1_TESTBIT);
mips_cpu_irq_init();
/*
* Initialize IC0, which is fixed per processor.
*/
imp = au1xxx_ic0_map;
for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
imp++;
}
/*
* Now set up the irq mapping for the board.
*/
imp = au1xxx_irq_map;
for (i = 0; i < au1xxx_nr_irqs; i++) {
setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
imp++;
}
set_c0_status(ALLINTS);
/* Board specific IRQ initialization.
*/
if (board_init_irq)
board_init_irq();
}
