/* This looks good enough to work, maybe */ static void vx800_sb_init(struct device *dev) { unsigned char enables; // enable the internal I/O decode enables = pci_read_config8(dev, 0x6C); enables |= 0x80; pci_write_config8(dev, 0x6C, enables); // Map 4MB of FLASH into the address space // pci_write_config8(dev, 0x41, 0x7f); // Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI // interrupts can be properly marked as level triggered. enables = pci_read_config8(dev, 0x40); enables |= 0x44; pci_write_config8(dev, 0x40, enables); /* DMA Line buffer control */ enables = pci_read_config8(dev, 0x42); enables |= 0xf0; pci_write_config8(dev, 0x42, enables); /* I/O recovery time */ pci_write_config8(dev, 0x4c, 0x44); /* ROM memory cycles go to LPC. */ pci_write_config8(dev, 0x59, 0x80); /* Set 0x5b to 0x01 to match Award */ //pci_write_config8(dev, 0x5b, 0x01); enables = pci_read_config8(dev, 0x5b); enables |= 0x01; pci_write_config8(dev, 0x5b, enables); /* Set Read Pass Write Control Enable */ pci_write_config8(dev, 0x48, 0x0c); /* Set 0x58 to 0x42 APIC and RTC. */ //pci_write_config8(dev, 0x58, 0x42); this cmd cause the irq0 can not be triggerd,since bit 5 was set to 0. enables = pci_read_config8(dev, 0x58); enables |= 0x41; // pci_write_config8(dev, 0x58, enables); /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); /* enable serial irq */ pci_write_config8(dev, 0x52, 0x9); /* dma */ pci_write_config8(dev, 0x53, 0x00); // Power management setup setup_pm(dev); /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ pci_write_config8(dev, 0x40, 0x54); // Start the rtc cmos_init(0); }
static void vt8235_init(struct device *dev) { unsigned char enables; printk(BIOS_DEBUG, "vt8235 init\n"); // enable the internal I/O decode enables = pci_read_config8(dev, 0x6C); enables |= 0x80; pci_write_config8(dev, 0x6C, enables); // Map 4MB of FLASH into the address space pci_write_config8(dev, 0x41, 0x7f); // Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI // interrupts can be properly marked as level triggered. enables = pci_read_config8(dev, 0x40); enables |= 0x45; pci_write_config8(dev, 0x40, enables); // Set 0x42 to 0xf0 to match Award bios enables = pci_read_config8(dev, 0x42); enables |= 0xf0; pci_write_config8(dev, 0x42, enables); /* Set 0x58 to 0x03 to match Award */ pci_write_config8(dev, 0x58, 0x03); /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */ enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); // Set bit 3 of 0x4a, to match award (dummy pci request) enables = pci_read_config8(dev, 0x4a); enables |= 0x08; pci_write_config8(dev, 0x4a, enables); // Set bit 3 of 0x4f to match award (use INIT# as cpu reset) enables = pci_read_config8(dev, 0x4f); enables |= 0x08; pci_write_config8(dev, 0x4f, enables); // Set 0x58 to 0x03 to match Award pci_write_config8(dev, 0x58, 0x03); /* enable serial irq */ pci_write_config8(dev, 0x52, 0x9); /* dma */ pci_write_config8(dev, 0x53, 0x00); // Power management setup setup_pm(dev); /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */ pci_write_config8(dev, 0x40, 0x54); // Start the rtc rtc_init(0); }