/*! Init primary accelerant */
status_t
intel_init_accelerant(int device)
{
TRACE(("intel_init_accelerant()\n"));
status_t status = init_common(device, false);
if (status != B_OK)
return status;
intel_shared_info &info = *gInfo->shared_info;
init_lock(&info.accelerant_lock, "intel extreme accelerant");
init_lock(&info.engine_lock, "intel extreme engine");
setup_ring_buffer(info.primary_ring_buffer, "intel primary ring buffer");
// determine head depending on what's already enabled from the BIOS
// TODO: it would be nicer to retrieve this data via DDC - else the
// display is gone for good if the BIOS decides to only show the
// picture on the connected analog monitor!
gInfo->head_mode = 0;
if (read32(INTEL_DISPLAY_B_PIPE_CONTROL) & DISPLAY_PIPE_ENABLED)
gInfo->head_mode |= HEAD_MODE_B_DIGITAL;
if (read32(INTEL_DISPLAY_A_PIPE_CONTROL) & DISPLAY_PIPE_ENABLED)
gInfo->head_mode |= HEAD_MODE_A_ANALOG;
uint32 lvds = read32(INTEL_DISPLAY_LVDS_PORT);
// If we have an enabled display pipe we save the passed information and
// assume it is the valid panel size..
// Later we query for proper EDID info if it exists, or figure something
// else out. (Default modes, etc.)
bool hasPCH = gInfo->shared_info->device_type.HasPlatformControlHub();
if ((hasPCH && (lvds & PCH_LVDS_DETECTED) != 0)
|| (!hasPCH && (lvds & DISPLAY_PIPE_ENABLED) != 0)) {
save_lvds_mode();
gInfo->head_mode |= HEAD_MODE_LVDS_PANEL;
}
TRACE(("head detected: %#x\n", gInfo->head_mode));
TRACE(("adpa: %08lx, dova: %08lx, dovb: %08lx, lvds: %08lx\n",
read32(INTEL_DISPLAY_A_ANALOG_PORT),
read32(INTEL_DISPLAY_A_DIGITAL_PORT),
read32(INTEL_DISPLAY_B_DIGITAL_PORT), read32(INTEL_DISPLAY_LVDS_PORT)));
status = create_mode_list();
if (status != B_OK) {
uninit_common();
return status;
}
return B_OK;
}
/*! Init primary accelerant */
status_t
intel_init_accelerant(int device)
{
CALLED();
status_t status = init_common(device, false);
if (status != B_OK)
return status;
intel_shared_info &info = *gInfo->shared_info;
init_lock(&info.accelerant_lock, "intel extreme accelerant");
init_lock(&info.engine_lock, "intel extreme engine");
setup_ring_buffer(info.primary_ring_buffer, "intel primary ring buffer");
TRACE("pipe control for: 0x%" B_PRIx32 " 0x%" B_PRIx32 "\n",
read32(INTEL_PIPE_CONTROL), read32(INTEL_PIPE_CONTROL));
// Probe all ports
status = probe_ports();
// On TRACE, dump ports and states
dump_ports();
if (status != B_OK)
ERROR("Warning: zero active displays were found!\n");
status = assign_pipes();
if (status != B_OK)
ERROR("Warning: error while assigning pipes!\n");
status = create_mode_list();
if (status != B_OK) {
uninit_common();
return status;
}
return B_OK;
}
