static int __devinit sh_pm_probe(struct platform_device *pdev)
{
int rc;
struct input_dev *ipdev;
pm_key = kzalloc(sizeof(struct msm_handset), GFP_KERNEL);
if (!pm_key)
return -ENOMEM;
ipdev = input_allocate_device();
if (!ipdev) {
rc = -ENOMEM;
goto err_alloc_input_dev;
}
input_set_drvdata(ipdev, pm_key);
pm_key->ipdev = ipdev;
if (pdev->dev.platform_data)
pm_key->hs_pdata = pdev->dev.platform_data;
if (pm_key->hs_pdata->hs_name)
ipdev->name = pm_key->hs_pdata->hs_name;
else
ipdev->name = DRIVER_SH_PM_NAME;
ipdev->id.vendor = 0x0001;
ipdev->id.product = 1;
ipdev->id.version = 1;
input_set_capability(ipdev, EV_KEY, KEY_POWER);
input_set_capability(ipdev, EV_KEY, KEY_END);
#if defined(CONFIG_TENKEY_KEYPAD) && (CONFIG_TENKEY_KEYPAD_SUBID == 2)
if((sh_boot_get_hw_revision()==0x0002) || (sh_boot_get_hw_revision()==0x0003))
{
input_set_capability(ipdev, EV_KEY, KEY_SAVE);
shext_hw_revision_cleck = true;
}
#endif
rc = input_register_device(ipdev);
if (rc) {
dev_err(&ipdev->dev,
"hs_probe: input_register_device rc=%d\n", rc);
goto err_reg_input_dev;
}
platform_set_drvdata(pdev, pm_key);
return 0;
err_reg_input_dev:
input_free_device(ipdev);
err_alloc_input_dev:
kfree(pm_key);
pm_key = NULL;
return rc;
}
static int __devinit gdsc_probe(struct platform_device *pdev)
{
static atomic_t gdsc_count = ATOMIC_INIT(-1);
struct regulator_init_data *init_data;
struct resource *res;
struct gdsc *sc;
uint32_t regval;
bool retain_mem, retain_periph;
int i, ret;
sc = devm_kzalloc(&pdev->dev, sizeof(struct gdsc), GFP_KERNEL);
if (sc == NULL)
return -ENOMEM;
init_data = of_get_regulator_init_data(&pdev->dev, pdev->dev.of_node);
if (init_data == NULL)
return -ENOMEM;
if (of_get_property(pdev->dev.of_node, "parent-supply", NULL))
init_data->supply_regulator = "parent";
ret = of_property_read_string(pdev->dev.of_node, "regulator-name",
&sc->rdesc.name);
if (ret)
return ret;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (res == NULL)
return -EINVAL;
sc->gdscr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (sc->gdscr == NULL)
return -ENOMEM;
sc->clock_count = of_property_count_strings(pdev->dev.of_node,
"qcom,clock-names");
if (sc->clock_count == -EINVAL) {
sc->clock_count = 0;
} else if (IS_ERR_VALUE(sc->clock_count)) {
dev_err(&pdev->dev, "Failed to get clock names\n");
return -EINVAL;
}
sc->clocks = devm_kzalloc(&pdev->dev,
sizeof(struct clk *) * sc->clock_count, GFP_KERNEL);
if (!sc->clocks)
return -ENOMEM;
for (i = 0; i < sc->clock_count; i++) {
const char *clock_name;
of_property_read_string_index(pdev->dev.of_node,
"qcom,clock-names", i,
&clock_name);
sc->clocks[i] = devm_clk_get(&pdev->dev, clock_name);
if (IS_ERR(sc->clocks[i])) {
int rc = PTR_ERR(sc->clocks[i]);
if (rc != -EPROBE_DEFER)
dev_err(&pdev->dev, "Failed to get %s\n",
clock_name);
return rc;
}
}
sc->rdesc.id = atomic_inc_return(&gdsc_count);
sc->rdesc.ops = &gdsc_ops;
sc->rdesc.type = REGULATOR_VOLTAGE;
sc->rdesc.owner = THIS_MODULE;
platform_set_drvdata(pdev, sc);
/*
* Disable HW trigger: collapse/restore occur based on registers writes.
* Disable SW override: Use hardware state-machine for sequencing.
*/
regval = readl_relaxed(sc->gdscr);
regval &= ~(HW_CONTROL_MASK | SW_OVERRIDE_MASK);
/* Configure wait time between states. */
regval &= ~(EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK);
regval |= EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
writel_relaxed(regval, sc->gdscr);
retain_mem = of_property_read_bool(pdev->dev.of_node,
"qcom,retain-mem");
sc->toggle_mem = !retain_mem;
retain_periph = of_property_read_bool(pdev->dev.of_node,
"qcom,retain-periph");
sc->toggle_periph = !retain_periph;
sc->toggle_logic = !of_property_read_bool(pdev->dev.of_node,
"qcom,skip-logic-collapse");
#if defined(CONFIG_MACH_TBS) && defined(CONFIG_ANDROID_ENGINEERING)
{
static sharp_smem_common_type *smemdata = NULL;
unsigned long hw_revision = sh_boot_get_hw_revision();
unsigned int version = socinfo_get_version();
const char* target_names_collapse[] = {
"gdsc_venus", "gdsc_mdss"
};
const char* target_names_retention[] = {
"gdsc_venus", "gdsc_mdss", "gdsc_oxili_gx"
};
if( smemdata == NULL ) {
smemdata = sh_smem_get_common_address();
}
if( (smemdata != NULL)
&& ((hw_revision == HW_VERSION_PP_1) || (hw_revision == HW_VERSION_PP_2)) ) {
if (smemdata->shdiag_rvcflg != SHDIAG_RVCFLG_ON) {
if ( (SOCINFO_VERSION_MAJOR(version) == 2) && (SOCINFO_VERSION_MINOR(version) == 2) ) {
int i = 0;
for(i=0; i<(sizeof(target_names_retention)/sizeof(target_names_retention[0])); i++) {
if( strcmp(sc->rdesc.name, target_names_retention[i]) == 0 ) {
break;
}
}
if( i != (sizeof(target_names_retention)/sizeof(target_names_retention[0])) ) {
if( retain_mem != true ) {
dev_err(&pdev->dev, "%s is forced to use retain_mem\n", sc->rdesc.name);
retain_mem = true;
sc->toggle_mem = !retain_mem;
}
if( retain_periph != true ) {
dev_err(&pdev->dev, "%s is forced to use retain_periph\n", sc->rdesc.name);
retain_periph = true;
sc->toggle_periph = !retain_periph;
}
}
for(i=0; i<(sizeof(target_names_collapse)/sizeof(target_names_collapse[0])); i++) {
if( strcmp(sc->rdesc.name, target_names_collapse[i]) == 0 ) {
break;
}
}
if( i != (sizeof(target_names_collapse)/sizeof(target_names_collapse[0])) ) {
if( sc->toggle_logic != false ) {
dev_err(&pdev->dev, "%s is forced to use skip_logic_collapse\n", sc->rdesc.name);
sc->toggle_logic = false;
}
}
}
}
}
}
#endif
if (!sc->toggle_logic) {
regval &= ~SW_COLLAPSE_MASK;
writel_relaxed(regval, sc->gdscr);
ret = readl_tight_poll_timeout(sc->gdscr, regval,
regval & PWR_ON_MASK, TIMEOUT_US);
if (ret) {
dev_err(&pdev->dev, "%s enable timed out\n",
sc->rdesc.name);
return ret;
}
}
for (i = 0; i < sc->clock_count; i++) {
if (retain_mem || (regval & PWR_ON_MASK))
clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_MEM);
else
clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_MEM);
if (retain_periph || (regval & PWR_ON_MASK))
clk_set_flags(sc->clocks[i], CLKFLAG_RETAIN_PERIPH);
else
clk_set_flags(sc->clocks[i], CLKFLAG_NORETAIN_PERIPH);
}
sc->rdev = regulator_register(&sc->rdesc, &pdev->dev, init_data, sc,
pdev->dev.of_node);
if (IS_ERR(sc->rdev)) {
dev_err(&pdev->dev, "regulator_register(\"%s\") failed.\n",
sc->rdesc.name);
return PTR_ERR(sc->rdev);
}
return 0;
}
void shswic_setup_ucdcnt_91411(void)
{
int ret = 0;
uint8_t hwRevision = 0x00;
uint8_t ucdcnt = 0x44; /* 0x40 : INTBEN */
/* 0x04 : USBDETCTRL */
bool vbregdisen = true;
hwRevision = sh_boot_get_hw_revision();
#ifdef CONFIG_HARDWARE_REV_TYPE_1_SWIC
switch(hwRevision)
{
case 0x6: /* REV_PP1 */
case 0x3: /* REV_PP15 */
case 0x7: /* REV_PP2 */
vbregdisen = true;
break;
default:
vbregdisen = false;
break;
}
#endif /* CONFIG_HARDWARE_REV_TYPE_1_SWIC */
#ifdef CONFIG_HARDWARE_REV_TYPE_2_SWIC
switch(hwRevision)
{
case 0x5: /* REV_ES1 */
case 0x6: /* REV_PP1 */
case 0x3: /* REV_PP15 */
case 0x7: /* REV_PP2 */
vbregdisen = true;
break;
default:
vbregdisen = false;
break;
}
#endif /* CONFIG_HARDWARE_REV_TYPE_2_SWIC */
if(vbregdisen)
{
ret = shswic_i2c_read(&ucdcnt, 1, SHSWIC_REG_UCDCNT);
if (ret == SHSWIC_SUCCESS)
{
ucdcnt |= 0x04; /* set USBDETCTRL FLG */
}
else
{
ucdcnt = 0x44;
}
}
else
{
ret = shswic_i2c_read(&ucdcnt, 1, SHSWIC_REG_UCDCNT);
if (ret == SHSWIC_SUCCESS)
{
ucdcnt &= 0xFE; /* clear DCDRETRY FLG */
}
else
{
ucdcnt = 0x40;
}
}
ret = shswic_i2c_write(&ucdcnt, 1, SHSWIC_REG_UCDCNT);
SHSWIC_DEBUG_LOG_L("shswic_setup_ucdcnt_91411 ret(%d) ucdcnt(0x%x)", ret, ucdcnt);
wake_lock(&shswic_sleep_wake_lock_91411);
usleep(30000);
wake_unlock(&shswic_sleep_wake_lock_91411);
ucdcnt |= 0x01; /* set DCDRETRY FLG */
ret = shswic_i2c_write(&ucdcnt, 1, SHSWIC_REG_UCDCNT);
SHSWIC_DEBUG_LOG_L("shswic_setup_ucdcnt_91411 ret(%d) ucdcnt(0x%x)", ret, ucdcnt);
}
static int pmic8058_kp_read_matrix(struct pmic8058_kp *kp, u16 *new_state,
u16 *old_state)
{
/* SHARP Add. use 1 Row Line. other key data clear. start */
#ifdef CONFIG_KEYBOARD_SCKEY
#if (defined(CONFIG_QWERTY_KEYPAD) || defined(CONFIG_QWERTY2_KEYPAD) || defined(CONFIG_QWERTY3_KEYPAD))
volatile int j,i,k = 0;
volatile int bits_changed1;
volatile int bits_changed2;
volatile int bits_changed_old1;
volatile int bits_changed_old2;
volatile int board_state;
volatile int result;
#else
int j;
#endif /* (defined(CONFIG_QWERTY_KEYPAD) || defined(CONFIG_QWERTY2_KEYPAD) || defined(CONFIG_QWERTY3_KEYPAD)) */
#endif /* #ifdef CONFIG_KEYBOARD_SCKEY */
/* SHARP Add. use 1 Row Line. end */
int rc, read_rows;
u8 scan_val;
static u8 rows[] = {
5, 6, 7, 8, 10, 10, 12, 12, 15, 15, 15, 18, 18, 18
};
if (kp->flags & KEYF_FIX_LAST_ROW &&
(kp->pdata->num_rows != PM8058_MAX_ROWS))
read_rows = rows[kp->pdata->num_rows - KEYP_CTRL_SCAN_ROWS_MIN
+ 1];
else
read_rows = kp->pdata->num_rows;
if (pm8058_rev(kp->pm_chip) > PM_8058_REV_1p0)
pmic8058_chk_sync_read(kp);
if (old_state)
rc = pmic8058_kp_read_data(kp, old_state, KEYP_OLD_DATA,
read_rows);
rc = pmic8058_kp_read_data(kp, new_state, KEYP_RECENT_DATA,
read_rows);
if (pm8058_rev(kp->pm_chip) > PM_8058_REV_1p0) {
/* 4 * 32KHz clocks */
udelay((4 * USEC_PER_SEC / KEYP_CLOCK_FREQ) + 1);
rc = pmic8058_kp_read(kp, &scan_val, KEYP_SCAN, 1);
scan_val &= 0xFE;
rc = pmic8058_kp_write_u8(kp, scan_val, KEYP_SCAN);
}
/* SHARP Add. use 1 Row Line. other key data clear. start */
#ifdef CONFIG_KEYBOARD_SCKEY
#if (defined(CONFIG_TENKEY_KEYPAD) || defined(CONFIG_TENKEY2_KEYPAD) || defined(CONFIG_TENKEY3_KEYPAD))
/* depend on target system */
for( j = 6; j <MATRIX_MAX_ROWS; j++)
{
if (old_state)
{
old_state[j] = 0xff;
}
new_state[j] = 0xff;
}
#elif (defined(CONFIG_QWERTY_KEYPAD) || defined(CONFIG_QWERTY2_KEYPAD) || defined(CONFIG_QWERTY3_KEYPAD))
result = sh_boot_get_hw_revision();
if( (result & 0x0002) == 0 ) {
board_state = 0;
} else {
board_state =1;
}
SHDBG_KEY_HAL(printk(KERN_DEBUG "[shkey]result:0x%x,board_state:0x%x\n", result ,board_state);)
/* depend on target system */
for( j = 10; j <MATRIX_MAX_ROWS; j++)
