static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
struct si_shader *shader,
struct si_shader_config *config)
{
uint64_t scratch_bo_size, scratch_needed;
scratch_bo_size = 0;
scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
if (sctx->compute_scratch_buffer)
scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
if (scratch_bo_size < scratch_needed) {
r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
sctx->compute_scratch_buffer =
si_resource_create_custom(&sctx->screen->b.b,
PIPE_USAGE_DEFAULT, scratch_needed);
if (!sctx->compute_scratch_buffer)
return false;
}
if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
if (si_shader_binary_upload(sctx->screen, shader))
return false;
r600_resource_reference(&shader->scratch_bo,
sctx->compute_scratch_buffer);
}
return true;
}
while(num_tile_pipes--) {
i = backend_map & item_mask;
mask |= (1<<i);
backend_map >>= item_width;
}
if (mask != 0) {
ctx->backend_mask = mask;
return;
}
}
/* otherwise backup path for older kernels */
/* create buffer for event data */
buffer = si_resource_create_custom(&ctx->screen->screen,
PIPE_USAGE_STAGING,
ctx->max_db*16);
if (!buffer)
goto err;
/* initialize buffer with zeroes */
results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE);
if (results) {
uint64_t va = 0;
memset(results, 0, ctx->max_db * 4 * 4);
ctx->ws->buffer_unmap(buffer->cs_buf);
/* emit EVENT_WRITE for ZPASS_DONE */
va = r600_resource_va(&ctx->screen->screen, (void *)buffer);
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0);
