/* Initialize arguments for the shader export intrinsic */
static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
struct tgsi_full_declaration *d,
unsigned index,
unsigned target,
LLVMValueRef *args)
{
struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
struct lp_build_context *uint =
&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
struct lp_build_context *base = &bld_base->base;
unsigned compressed = 0;
unsigned chan;
if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
int cbuf = target - V_008DFC_SQ_EXP_MRT;
if (cbuf >= 0 && cbuf < 8) {
compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
if (compressed)
si_shader_ctx->shader->spi_shader_col_format |=
V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
else
si_shader_ctx->shader->spi_shader_col_format |=
V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
}
static void declare_input(
struct radeon_llvm_context * radeon_bld,
unsigned input_index,
const struct tgsi_full_declaration *decl)
{
struct si_shader_context * si_shader_ctx =
si_shader_context(&radeon_bld->soa.bld_base);
if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
declare_input_vs(si_shader_ctx, input_index, decl);
} else if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
declare_input_fs(si_shader_ctx, input_index, decl);
} else {
fprintf(stderr, "Warning: Unsupported shader type,\n");
}
}
static void emit_fdiv(const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
struct si_shader_context *ctx = si_shader_context(bld_base);
emit_data->output[emit_data->chan] =
LLVMBuildFDiv(bld_base->base.gallivm->builder,
emit_data->args[0], emit_data->args[1], "");
/* Use v_rcp_f32 instead of precise division. */
if (HAVE_LLVM >= 0x0309 &&
!LLVMIsConstant(emit_data->output[emit_data->chan]))
LLVMSetMetadata(emit_data->output[emit_data->chan],
ctx->fpmath_md_kind, ctx->fpmath_md_2p5_ulp);
}
static LLVMValueRef fetch_constant(
struct lp_build_tgsi_context * bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type,
unsigned swizzle)
{
struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
struct lp_build_context * base = &bld_base->base;
const struct tgsi_ind_register *ireg = ®->Indirect;
unsigned idx;
LLVMValueRef args[2];
LLVMValueRef addr;
LLVMValueRef result;
if (swizzle == LP_CHAN_ALL) {
unsigned chan;
LLVMValueRef values[4];
for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
values[chan] = fetch_constant(bld_base, reg, type, chan);
return lp_build_gather_values(bld_base->base.gallivm, values, 4);
}
idx = reg->Register.Index * 4 + swizzle;
if (!reg->Register.Indirect)
return bitcast(bld_base, type, si_shader_ctx->constants[idx]);
args[0] = si_shader_ctx->const_resource;
args[1] = lp_build_const_int32(base->gallivm, idx * 4);
addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
args[1] = lp_build_add(&bld_base->uint_bld, addr, args[1]);
result = build_intrinsic(base->gallivm->builder, "llvm.SI.load.const", base->elem_type,
args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
return bitcast(bld_base, type, result);
}
