/**
* set spd mux to rad channel
*
* \param channel channel number (1...4)
* \return status code
*/
unsigned char spd_set_mux(unsigned char channel)
{
/* set mux signals depending to selected channel */
/* musing can be found in pericom switch datasheet */
switch (channel)
{
case SDRAM_AB:
/* S0: 0 S1: 0 AB0 -> Y */
signal_deactivate(&spd_i2c_mux[0]);
signal_deactivate(&spd_i2c_mux[1]);
break;
case SDRAM_CD:
/* S1: 1 S1: 0 AB1 -> Y */
signal_activate(&spd_i2c_mux[0]);
signal_deactivate(&spd_i2c_mux[1]);
break;
case SDRAM_EF:
/* S1: 0 S1: 1 AB2 -> Y */
signal_deactivate(&spd_i2c_mux[0]);
signal_activate(&spd_i2c_mux[1]);
break;
case SDRAM_GH:
/* S1: 1 S1: 1 AB3 -> Y */
signal_activate(&spd_i2c_mux[0]);
signal_activate(&spd_i2c_mux[1]);
break;
default:
/* select channel AB */
signal_deactivate(&spd_i2c_mux[0]);
signal_deactivate(&spd_i2c_mux[1]);
break;
}
return E_OK;
}
/**
* set bios flash wp
*
* \param bios_select bios select 1,2
* \param 1 - setting write protect, 0 - not write protected
* \return status code
*/
unsigned char bios_set_flash_wp(unsigned char bios_select, unsigned char setting)
{
/* set depending to input value */
if (bios_select == BIOS_SELECT_1)
{
if (setting == 0)
{
/* set bios 1 wp */
signal_activate(&sig_bios_wp[1]);
}
else
{
/* reset bios 1 wp */
signal_deactivate(&sig_bios_wp[1]);
}
}
else
{
if (setting == 0)
{
/* set bios 0 wp */
signal_activate(&sig_bios_wp[0]);
}
else
{
/* reset bios 0 wp */
signal_deactivate(&sig_bios_wp[0]);
}
}
/* return statuscode */
return E_OK;
}
NotebookNewNoteMenuItem::NotebookNewNoteMenuItem(const Notebook::Ptr & notebook)
// TRANSLATORS: %1%: boost format placeholder for the notebook name
: Gtk::ImageMenuItem(str(boost::format(_("New \"%1%\" Note")) % notebook->get_name()))
, m_notebook(notebook)
{
set_image(*manage(new Gtk::Image(IconManager::obj().get_icon(IconManager::NOTE_NEW, 16))));
signal_activate().connect(sigc::mem_fun(*this, &NotebookNewNoteMenuItem::on_activated));
}
Application::Application()
{
auto app = Gtk::Application::create("org.domag");
builder = std::make_unique<Builder>();
prepareView();
auto addContainerMenuItem = builder->getAddTopLevelContainerMenuItem();
addContainerMenuItem->signal_activate().connect(sigc::mem_fun(*this, &Application::openNewContainerDialog));
app->run(*builder->getMainWindow());
}
/**
* enable/disable IPMBL bus buffer
*/
unsigned char ipmb1_bus_ctrl(unsigned char bus, unsigned char control)
{
#ifdef CFG_CM
if (control == IPMB_ENABLE)
signal_activate(&sig_ipmb1en[bus]);
else
signal_deactivate(&sig_ipmb1en[bus]);
#endif
return E_OK;
}
RegisteredText::RegisteredText ( const Glib::ustring& label, const Glib::ustring& tip,
const Glib::ustring& key, Registry& wr, Inkscape::XML::Node* repr_in,
SPDocument * doc_in )
: RegisteredWidget<Text>(label, tip)
{
init_parent(key, wr, repr_in, doc_in);
setProgrammatically = false;
setText("");
_activate_connection = signal_activate().connect (sigc::mem_fun (*this, &RegisteredText::on_activate));
}
/**
* enable/disable IPMBL bus buffer
*/
void ipmbl_bus_ctrl(unsigned char amcsite, unsigned char control)
{
#ifdef CFG_CM
if (control == IPMB_ENABLE)
signal_activate(&sig_ipmblen[amcsite]);
else
signal_deactivate(&sig_ipmblen[amcsite]);
#endif
return;
}
/**
* Perform a fallback to the default nvram settings
* at next payload reboot
*
* \return active bios flash
*/
unsigned char bios_load_nvram_defaults(void)
{
/* set fpga register bit, to load nvram defaults */
signal_activate(&sig_cmos_soft_reset);
debug_uart_printf(DBG_GRP_FRU, 2, "Load NVRAM defaults at following boot\n");
/* only allow rtc reset, when payload is off */
/* this if part of the implementation is only needed for backwards compatibility */
if (!signal_read(&sig_payload_power))
{
/* set cmos clear */
signal_activate(&sig_cmos_clear);
/* wait for 5 ms */
util_wait_ms(5);
/* reset cmos clear */
signal_deactivate(&sig_cmos_clear);
}
return E_OK;
}
/**
* initialize external interrupt handling for EINT1
*/
void external_interrupt_init(void)
{
#ifdef CFG_FPGA
unsigned char tmpData = 0x00;
#endif
/* set edge sensivity for EINT1 external interrupt */
EXTMODE |= EINT1_ES;
/* set falling edge sensivity for EINT1 external interrupt */
EXTPOLAR = 0;
/* set interrupt vector entry for EINT1 external interrupt */
set_isr_handler(EINT1_IRQ, (void *)external_interrupt_isr, EINT1_IRQ_PRIO);
/* clear external interrupt EINT1 */
EXTINT |= EINT1_EN;
#ifdef CFG_FPGA
/* disable all interrupt sources */
spi_fpga_write(CFG_FPGA_INT_EN0, &tmpData);
#ifdef CFG_FPGA_INT_EN1
spi_fpga_write(CFG_FPGA_INT_EN1, &tmpData);
#endif
#if defined(CFG_PI_KCS) && !defined(CFG_PI_KCS_AUTO_INT)
/* clear KCS IRQ and enable it afterwards */
signal_int_clear(&sig_kcs_interrupt);
signal_activate(&sig_kcs_interrupt_enable);
#endif
#if defined(CFG_BIOS_ABU_UPDATE) && defined(CFG_MIC5603)
signal_activate(&sig_abu_interrupt_enable);
#endif
#endif /* CFG_FPGA */
}
MainTreeView::MainTreeView(std::vector<Player>& players_list) :
players_list(players_list)
{
//Create the Tree model:
m_refTreeModel = Gtk::ListStore::create(m_Columns);
set_model(m_refTreeModel);
//Fill the TreeView's model
updateTreeView();
//Add the TreeView's view columns:
append_column("Rank", m_Columns.m_col_rank);
append_column("ID", m_Columns.m_col_id);
append_column("Name", m_Columns.m_col_name);
append_column("Elo", m_Columns.m_col_elo);
append_column("K Coefficient", m_Columns.m_col_kcoeff);
//Fill popup menu:
auto item = Gtk::manage(new Gtk::MenuItem("_Edit", true));
item->signal_activate().connect(
sigc::mem_fun(*this, &MainTreeView::on_menu_file_popup_edit_player) );
m_Menu_Popup.append(*item);
item = Gtk::manage(new Gtk::MenuItem("_Add a Result", true));
item->signal_activate().connect(
sigc::mem_fun(*this, &MainTreeView::on_menu_file_popup_add_result) );
m_Menu_Popup.append(*item);
item = Gtk::manage(new Gtk::MenuItem("_Remove", true));
item->signal_activate().connect(
sigc::mem_fun(*this, &MainTreeView::on_menu_file_popup_remove_player) );
m_Menu_Popup.append(*item);
m_Menu_Popup.accelerate(*this);
m_Menu_Popup.show_all(); //Show all menu items when the menu pops up
}
/**
* This function triggers an interrupt to the payload
*
* \param rq request message
* \param rs response message
*/
void bmc_oem_trigger_os_interrupt(ipmbMSG_t *rq, ipmbMSG_t *rs)
{
/* check for valid iana */
if (check_iana(rq, rs))
{
return;
}
/* trigger interrupt */
signal_activate(&sig_diagnostic_interrupt);
rs->data_len = 1;
rs->data[0] = CC_COMPLETED_NORMALLY;
return;
}
/**
* bios select
* (Note: use carefully, because flash selection is not stored in EEPROM!)
*
* \param bios_select Bios selection
* \return bios selection
*/
unsigned char select_bios(unsigned char bios_select)
{
if (bios_select == BIOS_SELECT_1)
{
/* select bios 1 */
debug_uart_printf(DBG_GRP_FRU, 2, "\nSelect BIOS Flash 1\n");
signal_activate(&sig_bios_select);
return BIOS_SELECT_1;
}
else
{
/* select bios 0 */
debug_uart_printf(DBG_GRP_FRU, 2, "\nSelect BIOS Flash 0\n");
signal_deactivate(&sig_bios_select);
return BIOS_SELECT_0;
}
}
/** initializes the graceful shutdown
*
@param none :
*
@return : E_OK for success, none 0 for error
*
*******************************************************************************/
unsigned char graceful_shutdown_start(void)
{
/* - set timeout flag for payload / CM shutdown
* - ignore wrap around because change for this to happen is non-existent */
#ifdef ADV_OEM_INTEGRITY_SENSOR
start_shutdown_timer();
set_is_event_generation_flag(IS_IPMC_FW_GRACEFUL_SHUTDOWN, SET);
#endif
/* set shutdown timer */
fru_info.timeout = global_data.timer + (CFG_GF_SHUTDOWN_TIMEOUT * 10);
/* shut down payload (toggle Power button)*/
signal_activate(&sig_payload_shutdown);
GSD_DEBUG_PRINTF((DEBUG_UART,"graceful shutdown initiated...\n"));
return E_OK;
}
/**
* Initialize a graceful shutdown
*
* deactivate cpu sensors and push the internal powerbutton
*
* \return
* -#E_OK started successful
*/
unsigned char graceful_shutdown_start(void)
{
gp_timer_start(&gsd_timeout, oem_config.gf_timeout * configTICK_RATE_HZ);
/* reset gsd flag */
gsd_finished = 0;
gsd_active = 1;
/* disable dimm voltage sensors */
sdr_set_sensors_state(SENSOR_DEACTIVATE, SENSOR_DIMM_VOLTAGE_DEPENDENT);
/* shut down payload (toggle Power button) */
signal_activate(&sig_payload_pw_button);
debug_uart_printf(DBG_GRP_PAYLOAD, 2, "graceful shutdown initiated...\n");
return E_OK;
}
/**
* enable/disable IPMB0-A/B bus buffer when bus is free
*/
unsigned char ipmb0_bus_ctrl(unsigned char bus, unsigned char control)
{
/* enable is always allowed */
if (control == IPMB_ENABLE)
{
/* activate buffers */
signal_activate(&sig_ipmb0en[bus]);
}
/* control is disable */
else
{
/* check for isolation of both busses */
if (bus == IPMB0_A)
{
/* is IPMB0-B enabled? */
if (!(signal_read(&sig_ipmb0en[IPMB0_B])))
{
/* do not deactivate bus A */
return E_INVALID;
}
}
else
{
/* is IPMB0-A enabled? */
if (!(signal_read(&sig_ipmb0en[IPMB0_A])))
{
/* do not deactivate bus A */
return E_INVALID;
}
}
/* deactivate buffers */
signal_deactivate(&sig_ipmb0en[bus]);
}
return E_OK;
}
/**
* check dimm presence and voltage
*
* \return status code
*/
unsigned char spd_check_presence_and_voltage(void)
{
unsigned char i, reading;
dimm_power = 0;
/* walk through all dimms */
for (i = 0; i < SDRAM_MAX_DIMMS; i++)
{
/* read voltage support register if accessable */
if (spd_read_register(i, SDRAM_VOLTAGE_SUPPORT, &reading) == E_OK)
{
spd_initialized = 1;
/* set ddr module as populated */
ddr_modules[i].populated = 1;
/* calculate dimm power demand */
dimm_power += DIMM_POWER_DEMAND;
/* fill struct values with real voltages */
ddr_modules[i].voltage = reading & SDRAM_VOLTAGE_MASK;
/* get memory size */
spd_get_memory_values(i);
}
else
{
spd_initialized = 0;
debug_uart_printf(DBG_GRP_PAYLOAD, 2, "DIMM %d not populated\n",i);
/* set ddr module as not populated */
ddr_modules[i].populated = 0;
/* write 1.35V for compatibility if not populated */
ddr_modules[i].voltage = SDRAM_VOLTAGE_1_35;
}
}
/* if CPU0 dimm modules are all 1.35V */
if (ddr_modules[0].voltage == SDRAM_VOLTAGE_1_35 && ddr_modules[1].voltage == SDRAM_VOLTAGE_1_35 && ddr_modules[2].voltage == SDRAM_VOLTAGE_1_35 && ddr_modules[3].voltage == SDRAM_VOLTAGE_1_35)
{
unsigned short dependency = SENSOR_PAYLOAD_DEPENDENT | SENSOR_DIMM_VOLTAGE_DEPENDENT | SENSOR_CPU0_DEPENDENT;
thresholds_t new_thresholds = {160,150,125,176,187,246,0};
sdr_change_thresholds(&new_thresholds, dependency);
/* activate 1.35V for DIMMs CPU 0 */
signal_activate(&sig_ddr_voltage[0]);
}
else
{
/* activate 1.5V for DIMMs CPU 0 */
signal_deactivate(&sig_ddr_voltage[0]);
}
/* if CPU1 dimm modules are all 1.35V */
if (ddr_modules[4].voltage == SDRAM_VOLTAGE_1_35 && ddr_modules[5].voltage == SDRAM_VOLTAGE_1_35 && ddr_modules[6].voltage == SDRAM_VOLTAGE_1_35 && ddr_modules[7].voltage == SDRAM_VOLTAGE_1_35)
{
unsigned short dependency = SENSOR_PAYLOAD_DEPENDENT | SENSOR_DIMM_VOLTAGE_DEPENDENT | SENSOR_CPU1_DEPENDENT;
thresholds_t new_thresholds = {160,150,125,176,187,246,0};
sdr_change_thresholds(&new_thresholds, dependency);
/* activate 1.35V for DIMMs CPU 1 */
signal_activate(&sig_ddr_voltage[1]);
}
else
{
/* activate 1.5V for DIMMs CPU 1 */
signal_deactivate(&sig_ddr_voltage[1]);
}
return E_OK;
}
/**
* Task to send and receive IPMB messages over IPMB0-A and B to/from backplane.
*
* Every IPMI message is handled in a seperate ISR for IPMB0-A or IPMB0-B.
* Received messages from the backplane regardless of source (IPMB0-A or
* IPMB0-B) are put into the global queue ipmb0_recv_queue in the MCMC
* internal used IPMB format. IPMB messages to the backplane are send
* alternating to IPMB0-A and IPMB0-B. Task/Queue wait time calculation:
* a 10 byte message is handled within 1ms on 100kHz i2c bus
*/
void ipmb0_i2c_task(void *pvParameters)
{
ipmbMSG_t *message;
/* alternate Flag: 1 == IPMB0-A and 2 == IPMB0-B */
static int ipmb0_tx_bus = IPMB0_B;
/* alternate Flag: 1 == IPMB0-A and 2 == IPMB0-B */
static int ipmb0_rx_bus = IPMB0_A;
unsigned long timeout;
struct gp_timer timer_bus_fault_retry;
while (1)
{
#ifdef CFG_DEBUG_PERFORMANCE
perf_ipmb0_task_stack = uxTaskGetStackHighWaterMark(NULL);
unsigned char perf_temp;
perf_temp = uxQueueMessagesWaiting(ipmb0_rx_queue);
if (perf_temp > perf_ipmb0_rx_waiting)
perf_ipmb0_rx_waiting = perf_temp;
#endif
/* re-enable i2c buffer to retry communication */
if (gp_timer_once(&timer_bus_fault_retry))
{
/* reenable buffer just in local control mode */
if ((ipmb_control & (1 << IPMB0_A)) == 0)
{
signal_activate(&sig_ipmb0en[IPMB0_A]);
}
if ((ipmb_control & (1 << IPMB0_B)) == 0)
{
signal_activate(&sig_ipmb0en[IPMB0_B]);
}
}
/* get new message from ipmb0_rx_queue if last message has been sent */
if (get_new_ipmb0_message == IPMB_TX_BUFFER_FREE)
{
/* poll ipmb0_rx_queue for message, don't block */
if (xQueueReceive(ipmb0_rx_queue, &message, QUEUE_BLOCK_NONE))
{
/* convert and copy the internal IPMI message to IPMB format */
ipmb0_tx.length = convert_msg_to_ipmb(ipmb0_tx.buffer, message);
if (!ipmb0_tx.length) /* error */
{
/* print error message */
debug_uart_printf(DBG_GRP_IPMB0, 2, "ERR: %s: Invalid length in IPMB message.\n", __func__);
}
else
{
/* set TX buffer busy flag */
get_new_ipmb0_message = IPMB_TX_BUFFER_FULL;
timeout = xTaskGetTickCount();
retrycnt = 0;
}
/* free message buffer */
msg_free(message);
}
}
/* we have lost arbitration, repeat message */
if (get_new_ipmb0_message == IPMB_TX_BUFFER_REPEAT)
{
debug_uart_printf(DBG_GRP_IPMB0, 2, "%s: Arbitration lost, repeating.\n", __func__);
/* check if bus is free and repeat */
if ((ipmb0_flag[IPMB0_A] == I2C_FREE) && (ipmb0_flag[IPMB0_B] == I2C_FREE))
{
timeout = 0;
/* resend message */
get_new_ipmb0_message = IPMB_TX_BUFFER_FULL;
timeout = xTaskGetTickCount();
}
}
/* send message if there is one to be sent */
if ((get_new_ipmb0_message == IPMB_TX_BUFFER_FULL) && (((ipmb0_flag[IPMB0_A] == I2C_FREE) && (ipmb0_flag[IPMB0_B] != I2C_MASTER_WR)) || ((ipmb0_flag[IPMB0_A] != I2C_MASTER_WR) && (ipmb0_flag[IPMB0_B] == I2C_FREE))))
{
/* PICMG REQ 3.546 IPM Controllers should alternate
* transmission of messages on all enabled IPMBs */
if (ipmb0_tx_bus == IPMB0_A && signal_read(&sig_ipmb0en[IPMB0_B]))
{
ipmb0_tx_bus = IPMB0_B;
}
else if (ipmb0_tx_bus == IPMB0_B && signal_read(&sig_ipmb0en[IPMB0_A]))
{
ipmb0_tx_bus = IPMB0_A;
}
debug_uart_printf(DBG_GRP_IPMB0, 1, "<- IPMB-0%c: [", (ipmb0_tx_bus == IPMB0_A) ? 'A' : 'B');
for (int i = 0; i < ipmb0_tx.length; i++)
{
debug_uart_printf(DBG_GRP_IPMB0, 1, "%02X", ipmb0_tx.buffer[i]);
if (i != ipmb0_tx.length - 1)
{
debug_uart_printf(DBG_GRP_IPMB0, 1, " ");
}
}
debug_uart_printf(DBG_GRP_IPMB0, 1, "]\n");
/* IPMB0-A: Send if previous message has been sent and no slave RX */
{
/* Trigger sending IPMI message on IPMB0-A/B with START Flag on I2C-1/2 */
retrycnt++;
ipmb0_flag[ipmb0_tx_bus] = I2C_MASTER_WR;
if (ipmb0_tx_bus == IPMB0_A)
{
IPMB0A_I2CCONSET = STA;
}
else
{ /* ipmb0_tx_bus == IPMB0_B */
IPMB0B_I2CCONSET = STA;
}
}
}
else if (get_new_ipmb0_message == IPMB_TX_BUFFER_FULL)
{
if ((xTaskGetTickCount() - timeout) > I2C_ACK_TIMEOUT_TICKS)
{
/* no ack received, device not available */
/* abort transmission and discard message */
if (ipmb0_flag[0] == I2C_MASTER_WR)
{
IPMB0A_I2CCONSET = STO | AA;
debug_uart_printf(DBG_GRP_IPMB0, 2, "ERR: %s: Time out on IPMB0-A.\n", __func__);
/* disable buffer */
signal_deactivate(&sig_ipmb0en[IPMB0_A]);
}
if (ipmb0_flag[1] == I2C_MASTER_WR)
{
IPMB0B_I2CCONSET = STO | AA;
debug_uart_printf(DBG_GRP_IPMB0, 2, "ERR: %s: Time out on IPMB0-B.\n", __func__);
/* disable buffer */
signal_deactivate(&sig_ipmb0en[IPMB0_B]);
}
/* schedule buffer retry in 5 seconds */
gp_timer_start(&timer_bus_fault_retry, 5000);
ipmb0_flag[0] = I2C_FREE;
ipmb0_flag[1] = I2C_FREE;
get_new_ipmb0_message = IPMB_TX_BUFFER_FREE; /* discard message */
timeout = 0;
}
}
/* handle received IPMB0 messages if available */
/* alternate TX channels */
if (ipmb0_rx_bus == IPMB0_A)
ipmb0_rx_bus = IPMB0_B;
else
ipmb0_rx_bus = IPMB0_A;
/* handle IPMB0-A and IPMB0-B */
{
while (ipmb0_rx_list[ipmb0_rx_bus].read_pos != ipmb0_rx_list[ipmb0_rx_bus].write_pos)
{
if (ipmb0_rx_list[ipmb0_rx_bus].entry[ipmb0_rx_list[ipmb0_rx_bus].read_pos].status == IPMB_RX_BUF_FILLED)
{
/* allocate free message from global buffer */
if (!(message = msg_malloc()))
{
/* error */
uart_printf("ERR: %s: Could not msg_malloc() for message.\n", __func__);
}
else
{
/* convert IPMB message to internal IPMI format */
if (convert_ipmb_to_msg(ipmb0_rx_list[ipmb0_rx_bus].entry[ipmb0_rx_list[ipmb0_rx_bus].read_pos].buffer, ipmb0_rx_list[ipmb0_rx_bus].entry[ipmb0_rx_list[ipmb0_rx_bus].read_pos].length, message, global_data.bmc_ipmb_addr) != E_FAILURE)
{
/* forward message to the message hub */
if (xQueueSend(msg_hub_rx_queue, &message, QUEUE_BLOCK_10) != pdPASS)
{
/* queue size to small, change this */
uart_printf("ERR: %s: msg_hub_rx_queue full\n", __func__);
/* set error flag */
mon_queues |= MON_QUEUE_MSG_HUB_RX;
/* and discard message */
msg_free(message);
}
debug_uart_printf(DBG_GRP_IPMB0, 1, "-> IPMB-0%c: [%02X ", ipmb0_rx_bus ? 'B' : 'A', global_data.bmc_ipmb_addr);
for (int i = 0; i < ipmb0_rx_list[ipmb0_rx_bus].entry[ipmb0_rx_list[ipmb0_rx_bus].read_pos].length; i++)
{
debug_uart_printf(DBG_GRP_IPMB0, 1, "%02X", ipmb0_rx_list[ipmb0_rx_bus].entry[ipmb0_rx_list[ipmb0_rx_bus].read_pos].buffer[i]);
if (i != ipmb0_rx_list[ipmb0_rx_bus].entry[ipmb0_rx_list[ipmb0_rx_bus].read_pos].length - 1)
{
debug_uart_printf(DBG_GRP_IPMB0, 1, " ");
}
}
debug_uart_printf(DBG_GRP_IPMB0, 1, "]\n");
}
else
{
/* if message error discard message */
msg_free(message);
debug_uart_printf(DBG_GRP_IPMB0, 1, "ERR: %s: IPMB0 RX message error.\n", __func__);
}
}
}
/* free message buffer and go to the next in list */
ipmb0_rx_list[ipmb0_rx_bus].entry[ipmb0_rx_list[ipmb0_rx_bus].read_pos].status = IPMB_RX_BUF_EMPTY;
ipmb0_rx_list[ipmb0_rx_bus].entry[ipmb0_rx_list[ipmb0_rx_bus].read_pos].length = 0;
ipmb0_rx_list[ipmb0_rx_bus].read_pos = (ipmb0_rx_list[ipmb0_rx_bus].read_pos + 1) % IPMB0_RX_LIST_ENTRIES;
}
}
/* block task for some ticks if queue is empty */
if (uxQueueMessagesWaiting(ipmb0_rx_queue) == 0)
vTaskDelay((portTickType) IPMB_I2C_TASK_WAIT_TICKS);
} /* while (1) never ends */
}
/**
* BMC watchdog timer interrupt service routine
*/
void bmc_isr_wd_timer(void)
{
unsigned short pre_timer;
#ifdef CFG_SENSOR_BOOT_ERROR
sdr_data_t reading_data;
unsigned short sensor_data;
#endif
/* the watchdog timer is running with 100ms */
wd_timer.present_count--;
/* check only pre-timeout actions */
if (wd_timer.timer_action & 0x70)
{
if (wd_timer.pre_timeout)
{
pre_timer = wd_timer.present_count;
/* the pre-timeout timer is runnung with 1000ms */
/* pre-timeout timer expired */
if ((wd_timer.pre_timeout * 10) == pre_timer)
{
wd_timer.pretimeout_flag |= IPMB_WD_PRETO_FLAG;
if (wd_timer.timer_action & WD_PRETIMER_ACT_NMI)
{
bmc_oem_set_diag_int_reason (DIAG_INT_REASON_WATCHDOG, FALSE);
custom_payload_ctrl_send_cmd_from_ISR(PAYLOAD_CTRL_CMD_DIAG_INT);
}
if (!(wd_timer.timer_use & WD_TIMER_USE_DONT_LOG))
{
#ifdef CFG_SENSOR_BMCWDT
#ifdef CFG_CPCI8220
sensor_bmcwdt_set_state(WD_TIMER_ACT_TIMER_INT, (wd_timer.timer_action & 0x70) | (wd_timer.timer_use & 0x07));
#else
sensor_bmcwdt_set_state(wd_timer.timer_action & 0x07, (wd_timer.timer_use & 0x07)|0xF0);
#endif
#endif
}
}
}
}
/* timer expired? */
if (wd_timer.present_count == 0)
{
/* timer expired */
wd_timer.timer_use_flag |= (1 << (wd_timer.timer_use & 0x7));
/* stop timer */
watchdog_stop();
/* timer control register bit0 = 0 -> disable timer */
wd_timer.timer_use &= ~WD_TIMER_START;
if ((wd_timer.timer_action & 0x07) == WD_TIMER_ACT_HARD_RESET)
{
#ifdef CFG_CPCI
debug_uart_printf(DBG_GRP_WDT, 1,"BMC Watchdog: Reset Payload\n");
/* TODO wdt reset payload */
switch (wd_timer.timer_use & 0x07)
{
case WD_TIMER_USE_RSV_IWD:
{
unsigned char curr_bank = 0;
curr_bank = signal_read(&sig_norflash_sel);
if(oem_config.payload_flash_sel == curr_bank)
{
sensor_bmcwdt_set_state(WD_TIMER_ACT_HARD_RESET, (wd_timer.timer_use & 0x07)|0xF0);
custom_payload_ctrl_send_cmd_from_ISR(PAYLOAD_CTRL_CMD_INITIAL_WATCHDOG_COLD_RESET);
}
else
{
wd_timer.timer_action = WD_TIMER_ACT_PWR_DOWN;
#ifdef CFG_SENSOR_BOOT_ERROR
sensor_boot_error_state_get( &reading_data );
sensor_data = reading_data.data[2] + (reading_data.data[3]<<8);
if( !(sensor_data & (1 << BOOT_ERR_SEC_BANK_BOOT_FAIL)) )
{
sensor_boot_error_state_set(BOOT_ERR_SEC_BANK_BOOT_FAIL);
}
#endif
}
}
break;
default:
custom_payload_ctrl_send_cmd_from_ISR(PAYLOAD_CTRL_CMD_WATCHDOG_COLD_RESET);
break;
}
debug_uart_printf(DBG_GRP_WDT, 1, "BMC Watchdog: Timer Use = 0x%02X\n", wd_timer.timer_use);
#else /* #ifdef CFG_CPCI */
if ((wd_timer.timer_use & 0x07) == WD_TIMER_USE_BIOS_FRB2)
{
debug_uart_printf(DBG_GRP_WDT, 1, "Watchdog timeout\n");
#ifdef CFG_HPM1_BIOS_UPDATE
bios_redundancy_handle_watchdog_timeout();
/* restart watchdog timer only if payload power is on */
if (signal_read(&sig_payload_power))
{
watchdog_start();
wd_timer.present_count = CFG_BIOS_TIMEOUT;
/* timer control register bit0 = 0 -> enable timer */
wd_timer.timer_use |= WD_TIMER_START;
}
#endif
}
else
{
/* if payload power is on */
if (signal_read(&sig_payload_power))
{
#ifdef CFG_CM
signal_activate(&sig_payload_keep_enabled);
#endif
/* perform payload power cycle */
signal_deactivate(&sig_payload_power);
signal_activate(&sig_payload_power);
#ifdef CFG_CM
signal_deactivate(&sig_payload_keep_enabled);
#endif
}
}
#endif /* #ifdef CFG_CPCI */
#ifdef CFG_X86
sensor_nuvoton_reset_peci();
#endif
}
if ((wd_timer.timer_action & 0x07) == WD_TIMER_ACT_PWR_DOWN)
{
/* power down */
#ifdef CFG_CPCI
custom_payload_ctrl_send_cmd_from_ISR(PAYLOAD_CTRL_CMD_POWEROFF);
#else
signal_deactivate(&sig_payload_power);
#endif
debug_uart_printf(DBG_GRP_WDT, 1, "BMC Watchdog: Turn Off Payload\n");
}
if ((wd_timer.timer_action & 0x07) == WD_TIMER_ACT_PWR_CYCLE)
{
/* if payload power is on */
if (signal_read(&sig_payload_power))
{
#ifdef CFG_CM
signal_activate(&sig_payload_keep_enabled);
#endif
/* perform payload power cycle */
#ifdef CFG_CPCI
custom_payload_ctrl_send_cmd_from_ISR(PAYLOAD_CTRL_CMD_POWEROFF);
custom_payload_ctrl_send_cmd_from_ISR(PAYLOAD_CTRL_CMD_POWERON);
#else
signal_deactivate(&sig_payload_power);
signal_activate(&sig_payload_power);
#endif /* #ifdef CFG_CPCI */
#ifdef CFG_CM
signal_deactivate(&sig_payload_keep_enabled);
#endif
}
debug_uart_printf(DBG_GRP_WDT, 1, "BMC Watchdog: Power Cycle Payload\n");
}
if (!(wd_timer.timer_use & WD_TIMER_USE_DONT_LOG))
{
#ifdef CFG_SENSOR_BMCWDT
#ifdef CFG_CPCI
if ((wd_timer.timer_use & 0x07) != WD_TIMER_USE_RSV_IWD)
{
sensor_bmcwdt_set_state(wd_timer.timer_action & 0x07, (wd_timer.timer_use & 0x07)|0xF0);
}
#else
sensor_bmcwdt_set_state(wd_timer.timer_action & 0x07, (wd_timer.timer_use & 0x07)|0xF0);
#endif
#endif
}
else
{
/* clear do not log bit if timer expired, see IPMI 2.0 27.3 */
wd_timer.timer_use &= ~WD_TIMER_USE_DONT_LOG;
}
}
}
/**
* MMC payload power control state machine
*
* \param carrier_pwr_on carrier 12V payload power on/off measurement judgement
* \param pwr_seq_on onboard payload power sequencing done / power on
*/
void mmc_payload_pwr_states(unsigned char carrier_pwr_on, unsigned char pwr_seq_on)
{
/* handle states */
if (mmc_payload_state.old_st == mmc_payload_state.new_st)
{
/* state has not changed */
switch (mmc_payload_state.old_st)
{
case MMC_STATE_UNKWN:
/* detect current state */
if (!carrier_pwr_on)
{
/* 12V from carrier off */
mmc_payload_state.new_st = MMC_STATE_PWR_OFF;
}
else if (carrier_pwr_on && !pwr_seq_on)
{
/* 12V from carrier on, but onboard power not started */
mmc_payload_state.new_st = MMC_STATE_PWR_ON;
}
else if (carrier_pwr_on && pwr_seq_on)
{
/* 12V from carrier on and onboard power running */
mmc_payload_state.new_st = MMC_STATE_PWR_STABLE;
}
break;
case MMC_STATE_PWR_OFF:
/* 12V from carrier enabled and "off" state active for at least 9 seconds? */
if (carrier_pwr_on && gp_timer_expired(&timer_payload_pwr))
{
/* start onboard power */
mmc_payload_state.new_st = MMC_STATE_PWR_ON;
}
break;
case MMC_STATE_PWR_ON:
/* onboard power running for at least six seconds */
if (gp_timer_expired(&timer_payload_pwr))
{
/* move to onboard power stable */
mmc_payload_state.new_st = MMC_STATE_PWR_STABLE;
}
/* don't waste time if power sequence is done already */
else if (carrier_pwr_on && pwr_seq_on)
{
mmc_payload_state.new_st = MMC_STATE_PWR_STABLE;
}
break;
case MMC_STATE_PWR_STABLE:
/* check for payload system resets and any pending update actions */
#ifdef CFG_x86
fru_check_system_reset();
#endif
/* deactivation of payload - onboard power disabled */
if (!signal_read(&sig_payload_power))
{
/* onboard power disabled */
mmc_payload_state.new_st = MMC_STATE_PWR_OFF;
}
/* carrier power gone by mistake (onboard power enable still on) */
else if (!carrier_pwr_on && signal_read(&sig_payload_power))
{
/* 12V carrier power fail */
mmc_payload_state.new_st = MMC_STATE_PWR_FAIL;
}
break;
case MMC_STATE_PWR_FAIL:
/* hot swap handle open */
if (!signal_read(&sig_hs_handle))
{
/* payload power enable still on */
if (signal_read(&sig_payload_power))
{
/* switch off onboard power enable */
//fru_payload_poweroff();
}
}
/* payload power disabled? */
if (!signal_read(&sig_payload_power))
{
/* turn off red OOS LED */
led_set(LED_ID_1, LED_FUNC_OFF, 0);
/* return to normal payload power off state */
mmc_payload_state.new_st = MMC_STATE_PWR_OFF;
}
break;
default:
/* unknown state, set back to valid state */
mmc_payload_state.new_st = MMC_STATE_UNKWN;
break;
}
}
else
{
/* state has changed */
switch (mmc_payload_state.new_st)
{
case MMC_STATE_UNKWN:
/* store time */
uptime_payload_pwr = uptime();
break;
case MMC_STATE_PWR_OFF:
/* store payload power off start time */
uptime_payload_pwr = uptime();
gp_timer_start(&timer_payload_pwr, 9 * configTICK_RATE_HZ);
#ifdef CFG_BIOS_FLASH
/* check if there's BIOS redundancy work to do */
bios_redundancy_handle_update();
#endif
#ifdef CFG_IRTM
signal_deactivate(&sig_rtm_ready);
#endif
break;
case MMC_STATE_PWR_ON:
/* switch on payload power sequencing */
fru_payload_poweron();
/* store payload power on start time */
uptime_payload_pwr = uptime();
gp_timer_start(&timer_payload_pwr, 6 * configTICK_RATE_HZ);
break;
case MMC_STATE_PWR_STABLE:
#ifdef CFG_IRTM
signal_activate(&sig_rtm_ready);
#endif
/* store payload power stable start time */
uptime_payload_pwr = uptime();
break;
case MMC_STATE_PWR_FAIL:
#ifndef CFG_IRTM
/* turn on red OOS LED */
led_set(LED_ID_1, LED_FUNC_ON, 0);
#ifdef ADV_OEM_INTEGRITY_SENSOR
sensor_integrity_send_event(IS_HW, IS_ACTION_PAYLOAD_PWR, IS_FAIL);
#endif
#endif /* !CFG_IRTM */
/* store payload power fail start time */
uptime_payload_pwr = uptime();
break;
default:
/* unknown state, go back to unknown state */
mmc_payload_state.new_st = MMC_STATE_UNKWN;
break;
}
/* save new state */
mmc_payload_state.old_st = mmc_payload_state.new_st;
}
}
/**
* This function handles the OEM command to write a specific configuration
* from the EEPROM
*
* \param rq request message
* \param rs response message
*/
void bmc_oem_write_config_setting(ipmbMSG_t *rq, ipmbMSG_t *rs)
{
#ifdef CFG_HPM1_BIOS_SETTING_UPDATE
unsigned short section_good;
#endif
unsigned char safe_oem = 1;
/* Device
* Port
* SATA FLASH: 0x02
* - WRITE PROTECT 0x00
* BIOS FLASH: 0x03
* - IMAGE SEL 0x00
* - NVRAM SEL 0x01
* - NVRAM ACT 0x02
* LAN CONTROLLER: 0x04
* - INTERFACE 0x00
* - CHANNEL PRIO 0x01
* RTC: 0x07
* - SYNC 0x00
* FPGA: 0x08
* - COM1 MUX 0x00
* - COM2 MUX 0x01
* - IPMC MUX 0x02
* PCIE: 0x0B
* - RTM 0x00
* - FMM 0x01
* CLI: 0x0C
* - UART BAUDRATE 0x00
* - UART ENABLE 0x01
* IRQ: 0x0D
* - PROC HOT 0x00
* TIMER: 0x0E
* - CM TIMEOUT 0x00
* - GF TIMEOUT 0x01
*/
/* check for valid iana and fill iana in response */
if (check_iana(rq, rs))
{
/* invalid request */
return;
}
/* check if request length is valid */
else if (rq->data_len != 6)
{
rs->data[0] = CC_REQ_DATALEN_INVALID;
rs->data_len = 4;
return;
}
/* IANA valid */
else
{
rs->data[0] = CC_COMPLETED_NORMALLY;
rs->data_len = 4;
/* switch depending to setting */
switch (rq->data[3])
{
#ifdef CFG_SATA_FLASH
/* write sata flash write protection bit */
case SETTING_SATA_FLASH_WP:
switch (rq->data[4])
{
case PORT_SATA_FLASH_1:
/* check if setting is valid */
if (rq->data[5] == 0x00)
{
/* deactivate write protection */
signal_deactivate(&sig_sata_wp);
}
else if (rq->data[5] == 0x01)
{
/* set write protection */
signal_activate(&sig_sata_wp);
}
else
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
break;
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
#endif /* CFG_SATA_FLASH */
#ifdef CFG_BIOS_FLASH
case SETTING_BIOS:
switch (rq->data[4])
{
case PORT_BIOS_SELECT:
/* check if setting is valid */
if (rq->data[5] > 0)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
if (bios_switch_flash() != E_OK)
{
rs->data[0] = CC_NOT_SUPPORTED_IN_PRESENT_STATE;
rs->data_len = 1;
return;
}
/* read out bios versions */
bios_redundancy_switch_eeprom_versions();
safe_oem = 0;
break;
#ifdef CFG_HPM1_BIOS_SETTING_UPDATE
case PORT_NVRAM_UPDATE_SELECT:
/* check if setting is valid */
if (rq->data[5] >= CFG_NVRAM_AREA_MAX)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.update_nvram = rq->data[5];
break;
case PORT_NVRAM_ACTIVATE_SELECT:
/* check if setting is valid */
if (rq->data[5] >= CFG_NVRAM_AREA_MAX)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
/* check if activation section is good */
spi_eeprom_safe_area_read(HPM_COMPONENT_DATA_OFFSET +
HPM_NVRAM_DATA_OFFSET + EEPROM_HPM_COMP_SPEC_OFFS, 2,
(unsigned char*)§ion_good);
/* set section to not good */
if (section_good & (1 << rq->data[5]))
{
oem_config.activate_nvram = rq->data[5];
hpm_nvram_do_activate(); /* XXX: return code */
}
else
{
rs->data[0] = CC_REQUESTED_DATA_NOT_PRESENT;
rs->data_len = 1;
return;
}
break;
#endif /* CFG_HPM1_BIOS_SETTING_UPDATE */
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
#endif /* CFG_BIOS_FLASH */
#ifdef CFG_LAN
case SETTING_LAN_CONTROLLER:
switch (rq->data[4])
{
case PORT_LAN_INTERFACE:
/* check if setting is valid */
if (rq->data[5] > NCSI_LAN_BI)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.lan_intf_sel = rq->data[5];
break;
case PORT_LAN_CHAN_PRIO:
/* check if setting is valid */
if (rq->data[5] > NCSI_CHAN_SEL_INTF2_ONLY)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.lan_chan_prio = rq->data[5];
break;
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
#endif /* CFG_LAN */
#ifdef ADV_OEM_FAILURE_RETRY
case SETTING_FAILURE_RETRIES:
switch (rq->data[4])
{
case PORT_POWER_FAILURE:
oem_config.fail_retries_pwr = rq->data[5];
break;
case PORT_TEMP_FAILURE:
oem_config.fail_retries_temp = rq->data[5];
break;
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
#endif /* ADV_OEM_FAILURE_RETRY */
case SETTING_MISC_SETTINGS:
switch (rq->data[4])
{
#ifdef CFG_POWER_BUDGETING
case PORT_POWER_BUDGETING:
/* check if setting is valid */
if (rq->data[5] > 1 && rq->data[5] != DYN_POW_BUDGET_FORCE_LOW)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.power_budget = rq->data[5];
break;
#endif /* CFG_POWER_BUDGETING */
#ifdef REDRIVER_UPDATE_CHANNEL
case PORT_UPDATE_CHANNEL:
/* check if setting is valid */
if ((rq->data[5] != UPDATE_CHANNEL_ON) && (rq->data[5] != UPDATE_CHANNEL_OFF))
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.update_chan_offset = rq->data[5];
break;
#endif /* REDRIVER_UPDATE_CHANNEL */
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
#ifdef ADV_OEM_RTC_SYNC
#ifdef CFG_ATCA
case SETTING_RTC:
switch (rq->data[4])
{
case PORT_TIME_SYNC_ENABLE:
/* check if setting is in allowed range */
if (rq->data[5] > RTC_PAYLOAD_ON)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.rtc_time_sync = rq->data[5];
break;
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
#endif
#endif /* ADV_OEM_RTC_SYNC */
case SETTING_FPGA:
switch (rq->data[4])
{
#ifdef CFG_UART_MUX
case PORT_COM1_MUX:
/* check if setting is valid */
#ifdef CFG_ATCA
if ((rq->data[5] > 5) && (rq->data[5] != 0x0F))
#elif defined (CFG_MMC)
if (rq->data[5] > 3)
#endif
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.uart_mux1 = rq->data[5];
custom_set_uart_mux();
break;
case PORT_COM2_MUX:
/* check if setting is valid */
#ifdef CFG_ATCA
if (rq->data[5] > 4)
#elif defined (CFG_MMC)
if (rq->data[5] > 3)
#endif
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.uart_mux2 = rq->data[5];
custom_set_uart_mux();
break;
#ifdef ADV_CLI_SWITCHING
case PORT_BMC_MUX:
/* check if setting is valid */
#ifdef CFG_ATCA
if (rq->data[5] > 4)
#elif defined (CFG_MMC)
if (rq->data[5] > 3)
#endif
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.uart_mux_bmc = rq->data[5];
custom_set_uart_mux();
break;
#endif
#endif /* CFG_UART_MUX */
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
case SETTING_PCI_E_SPLITTING:
switch (rq->data[4])
{
#ifdef ADV_OEM_RTM_PCIE_CONFIG
case PORT_PCIE_RTM:
/* check if setting is valid */
if (rq->data[5] > PCIE_SPLITTING_x4_x4_x4_x4)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.pcie_rtm_conf = rq->data[5];
break;
#endif /* ADV_OEM_RTM_PCIE_CONFIG */
#if defined (I2C_BUS_MM) && (CFG_NUM_MMS_USED > 0)
#ifdef ADV_OEM_FMM_PCIE_CONFIG
case PORT_PCIE_FMM1:
/* check if setting is valid */
if (rq->data[5] > PCIE_SPLITTING_x4_x4_x4_x4)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.pcie_fmm_conf = rq->data[5];
break;
#endif
#endif
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
case SETTING_CLI:
switch (rq->data[4])
{
case PORT_UART_BAUDRATE:
/* check if setting is valid */
if (rq->data[5] > 5)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
oem_config.cli_baudrate = rq->data[5];
break;
#ifdef ADV_CLI_SWITCHING
case PORT_UART_ENABLE:
/* check if setting is valid */
if (rq->data[5] > 1)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
if (rq->data[5] == 0x00)
{
cli_uart_disable(CLI_UART);
}
else
{
cli_uart_enable(CLI_UART);
}
oem_config.cli_uart_enable = rq->data[5];
break;
#endif
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
case SETTING_IRQ:
switch (rq->data[4])
{
#ifdef ADV_OEM_PROC_HOT_IRQ
case PORT_PROC_HOT:
/* check if setting is valid */
if (rq->data[5] > 1)
{
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
return;
}
if (rq->data[5])
{
signal_activate(&sig_proc_hot_enable[0]);
signal_activate(&sig_proc_hot_enable[1]);
}
else
{
signal_deactivate(&sig_proc_hot_enable[0]);
signal_deactivate(&sig_proc_hot_enable[1]);
}
oem_config.proc_hot_irq = rq->data[5];
break;
#endif /* ADV_OEM_PROC_HOT_IRQ */
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
case SETTING_TIMER:
/* CM Configuration */
switch (rq->data[4])
{
#ifdef CFG_CM
case PORT_CM_TIMEOUT:
/* Values between 0 and 255 are possible! */
oem_config.cm_timeout= rq->data[5];
break;
#endif /* CFG_CM */
#ifdef OEM_GF_SHUTDOWN_TIMEOUT_DEFAULT
case PORT_GF_TIMEOUT:
/* Values between 0 and 255 are possible! */
oem_config.gf_timeout= rq->data[5];
break;
#endif
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
#ifdef CFG_CPCI
/* Payload boot bank selection */
case SETTING_PAYLOAD_FLASH:
switch (rq->data[4])
{
case PORT_CURR_FLASH_BANK_SEL:
switch (rq->data[5])
{
case PAYLOAD_FLASH_BANK0:
signal_deactivate(&sig_norflash_sel);
break;
case PAYLOAD_FLASH_BANK1:
signal_activate(&sig_norflash_sel);
break;
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
case PORT_NEXT_FLASH_BANK_SEL:
switch (rq->data[5])
{
case PAYLOAD_FLASH_BANK0:
oem_config.payload_flash_sel_for_next = rq->data[5];
break;
case PAYLOAD_FLASH_BANK1:
oem_config.payload_flash_sel_for_next = rq->data[5];
break;
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
break;
#endif /* #ifdef CFG_CPCI */
default:
rs->data[0] = CC_PARAMETER_OUT_OF_RANGE;
rs->data_len = 1;
break;
}
/* store new value to EEPROM section */
if (safe_oem)
{
if (save_oem_config() != E_OK)
{
rs->data[0] = CC_UNDEFINED;
rs->data_len = 1;
}
}
return;
}
}