t_stat sage_translateaddr(t_addr in,t_addr* out, IOHANDLER** ioh,int rw,int fc,int dma)
{
static uint32 bptype[] = { R_BKPT_SPC|SWMASK('R'), W_BKPT_SPC|SWMASK('W') };
t_addr ma = in & addrmask;
if (sim_brk_summ && sim_brk_test(ma, bptype[rw])) return STOP_IBKPT;
return m68k_translateaddr(in,out,ioh,rw,fc,dma);
}
t_stat sim_instr (void)
{
t_stat r = 0;
uint32 oPC;
/* Restore register state */
PC = PC & AMASK; /* mask PC */
sim_cancel_step (); /* defang SCP step */
if (lgp21_sov) { /* stop sense pending? */
lgp21_sov = 0;
if (!OVF) /* ovf off? skip */
PC = (PC + 1) & AMASK;
else OVF = 0; /* on? reset */
}
/* Main instruction fetch/decode loop */
do {
if (sim_interval <= 0) { /* check clock queue */
if ((r = sim_process_event ()))
break;
}
if (delay > 0) { /* delay to next instr */
delay = delay - 1; /* count down delay */
sim_interval = sim_interval - 1;
continue; /* skip execution */
}
if (sim_brk_summ && /* breakpoint? */
sim_brk_test (PC, SWMASK ('E'))) {
r = STOP_IBKPT; /* stop simulation */
break;
}
IR = Read (oPC = PC); /* get instruction */
PC = (PC + 1) & AMASK; /* increment PC */
sim_interval = sim_interval - 1;
if ((r = cpu_one_inst (oPC, IR))) { /* one instr; error? */
if (r == STOP_STALL) { /* stall? */
PC = oPC; /* back up PC */
delay = r = 0; /* no delay */
}
else break;
}
if (sim_step && (--sim_step <= 0)) /* do step count */
r = SCPE_STOP;
} while (r == 0); /* loop until halted */
pcq_r->qptr = pcq_p; /* update pc q ptr */
return r;
}
t_stat sim_instr (void)
{
t_stat reason = 0;
sim_cancel_step (); /* defang SCP step */
/* Main instruction fetch/decode loop */
do {
if (sim_interval <= 0) { /* check clock queue */
#if !UNIX_PLATFORM
if ((reason = sim_poll_kbd()) == SCPE_STOP) { /* poll on platforms without reliable signalling */
break;
}
#endif
if ((reason = sim_process_event ()))
break;
}
if (sim_brk_summ && /* breakpoint? */
sim_brk_test (*C, SWMASK ('E'))) {
reason = STOP_IBKPT; /* stop simulation */
break;
}
/* Increment current instruction */
*C = (*C + 1) & AMASK;
/* Get present instruction */
C[1] = Read (*C);
Staticisor = C[1] & IMASK; /* get instruction */
sim_interval = sim_interval - 1;
if ((reason = cpu_one_inst (*C, Staticisor))) { /* one instr; error? */
break;
}
if (sim_step && (--sim_step <= 0)) /* do step count */
reason = SCPE_STOP;
} while (reason == 0); /* loop until halted */
return reason;
}
