static int ma600_change_speed(struct sir_dev *dev, unsigned speed)
{
u8 byte;
IRDA_DEBUG(2, "%s(), speed=%d (was %d)\n", __FUNCTION__,
speed, dev->speed);
/* dongle already reset, dongle and port at default speed (9600) */
/* Set RTS low for 1 ms */
sirdev_set_dtr_rts(dev, TRUE, FALSE);
mdelay(1);
/* Write control byte */
byte = get_control_byte(speed);
sirdev_raw_write(dev, &byte, sizeof(byte));
/* Wait at least 10ms: fake wait_until_sent - 10 bits at 9600 baud*/
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(msecs_to_jiffies(15)); /* old ma600 uses 15ms */
#if 1
/* read-back of the control byte. ma600 is the first dongle driver
* which uses this so there might be some unidentified issues.
* Disable this in case of problems with readback.
*/
sirdev_raw_read(dev, &byte, sizeof(byte));
if (byte != get_control_byte(speed)) {
WARNING("%s(): bad control byte read-back %02x != %02x\n",
__FUNCTION__, (unsigned) byte,
(unsigned) get_control_byte(speed));
return -1;
}
else
IRDA_DEBUG(2, "%s() control byte write read OK\n", __FUNCTION__);
#endif
/* Set DTR, Set RTS */
sirdev_set_dtr_rts(dev, TRUE, TRUE);
/* Wait at least 10ms */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(msecs_to_jiffies(10));
/* dongle is now switched to the new speed */
dev->speed = speed;
return 0;
}
static int girbil_reset(struct sir_dev *dev)
{
unsigned state = dev->fsm.substate;
unsigned delay = 0;
u8 control = GIRBIL_TXEN | GIRBIL_RXEN;
int ret = 0;
IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
switch (state) {
case SIRDEV_STATE_DONGLE_RESET:
/* Reset dongle */
sirdev_set_dtr_rts(dev, TRUE, FALSE);
/* Sleep at least 5 ms */
delay = 20;
state = GIRBIL_STATE_WAIT1_RESET;
break;
case GIRBIL_STATE_WAIT1_RESET:
/* Set DTR and clear RTS to enter command mode */
sirdev_set_dtr_rts(dev, FALSE, TRUE);
delay = 20;
state = GIRBIL_STATE_WAIT2_RESET;
break;
case GIRBIL_STATE_WAIT2_RESET:
/* Write control byte */
sirdev_raw_write(dev, &control, 1);
delay = 20;
state = GIRBIL_STATE_WAIT3_RESET;
break;
case GIRBIL_STATE_WAIT3_RESET:
/* Go back to normal mode */
sirdev_set_dtr_rts(dev, TRUE, TRUE);
dev->speed = 9600;
break;
default:
IRDA_ERROR("%s(), undefined state %d\n", __FUNCTION__, state);
ret = -1;
break;
}
dev->fsm.substate = state;
return (delay > 0) ? delay : ret;
}
static int girbil_reset(struct sir_dev *dev)
{
unsigned state = dev->fsm.substate;
unsigned delay = 0;
u8 control = GIRBIL_TXEN | GIRBIL_RXEN;
int ret = 0;
IRDA_DEBUG(2, "%s()\n", __func__);
switch (state) {
case SIRDEV_STATE_DONGLE_RESET:
sirdev_set_dtr_rts(dev, TRUE, FALSE);
delay = 20;
state = GIRBIL_STATE_WAIT1_RESET;
break;
case GIRBIL_STATE_WAIT1_RESET:
sirdev_set_dtr_rts(dev, FALSE, TRUE);
delay = 20;
state = GIRBIL_STATE_WAIT2_RESET;
break;
case GIRBIL_STATE_WAIT2_RESET:
sirdev_raw_write(dev, &control, 1);
delay = 20;
state = GIRBIL_STATE_WAIT3_RESET;
break;
case GIRBIL_STATE_WAIT3_RESET:
sirdev_set_dtr_rts(dev, TRUE, TRUE);
dev->speed = 9600;
break;
default:
IRDA_ERROR("%s(), undefined state %d\n", __func__, state);
ret = -1;
break;
}
dev->fsm.substate = state;
return (delay > 0) ? delay : ret;
}
static int toim3232_change_speed(struct sir_dev *dev, unsigned speed)
{
unsigned state = dev->fsm.substate;
unsigned delay = 0;
u8 byte;
static int ret = 0;
IRDA_DEBUG(2, "%s()\n", __func__);
switch(state) {
case SIRDEV_STATE_DONGLE_SPEED:
/* Figure out what we are going to send as a control byte */
switch (speed) {
case 2400:
byte = TOIM3232_PW|TOIM3232_2400;
break;
default:
speed = 9600;
ret = -EINVAL;
/* fall thru */
case 9600:
byte = TOIM3232_PW|TOIM3232_9600;
break;
case 19200:
byte = TOIM3232_PW|TOIM3232_19200;
break;
case 38400:
byte = TOIM3232_PW|TOIM3232_38400;
break;
case 57600:
byte = TOIM3232_PW|TOIM3232_57600;
break;
case 115200:
byte = TOIM3232_115200;
break;
}
/* Set DTR, Clear RTS: Go into baud programming mode */
sirdev_set_dtr_rts(dev, TRUE, FALSE);
/* Wait at least 7us */
udelay(14);
/* Write control byte */
sirdev_raw_write(dev, &byte, 1);
dev->speed = speed;
state = TOIM3232_STATE_WAIT_SPEED;
delay = toim3232delay;
break;
case TOIM3232_STATE_WAIT_SPEED:
/* Have transmitted control byte * Wait for 'at least 1us' */
udelay(14);
/* Set DTR, Set RTS: Go into normal data mode */
sirdev_set_dtr_rts(dev, TRUE, TRUE);
/* Wait (TODO: check this is needed) */
udelay(50);
break;
default:
printk(KERN_ERR "%s - undefined state %d\n", __func__, state);
ret = -EINVAL;
break;
}
dev->fsm.substate = state;
return (delay > 0) ? delay : ret;
}
static int girbil_change_speed(struct sir_dev *dev, unsigned speed)
{
unsigned state = dev->fsm.substate;
unsigned delay = 0;
u8 control[2];
static int ret = 0;
IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
/* dongle alread reset - port and dongle at default speed */
switch(state) {
case SIRDEV_STATE_DONGLE_SPEED:
/* Set DTR and Clear RTS to enter command mode */
sirdev_set_dtr_rts(dev, FALSE, TRUE);
udelay(25); /* better wait a little while */
ret = 0;
switch (speed) {
default:
ret = -EINVAL;
/* fall through */
case 9600:
control[0] = GIRBIL_9600;
break;
case 19200:
control[0] = GIRBIL_19200;
break;
case 34800:
control[0] = GIRBIL_38400;
break;
case 57600:
control[0] = GIRBIL_57600;
break;
case 115200:
control[0] = GIRBIL_115200;
break;
}
control[1] = GIRBIL_LOAD;
/* Write control bytes */
sirdev_raw_write(dev, control, 2);
dev->speed = speed;
state = GIRBIL_STATE_WAIT_SPEED;
delay = 100;
break;
case GIRBIL_STATE_WAIT_SPEED:
/* Go back to normal mode */
sirdev_set_dtr_rts(dev, TRUE, TRUE);
udelay(25); /* better wait a little while */
break;
default:
IRDA_ERROR("%s - undefined state %d\n", __FUNCTION__, state);
ret = -EINVAL;
break;
}
dev->fsm.substate = state;
return (delay > 0) ? delay : ret;
}
static int tekram_change_speed(struct sir_dev *dev, unsigned speed)
{
unsigned state = dev->fsm.substate;
unsigned delay = 0;
u8 byte;
static int ret = 0;
IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
switch(state) {
case SIRDEV_STATE_DONGLE_SPEED:
switch (speed) {
default:
speed = 9600;
ret = -EINVAL;
/* fall thru */
case 9600:
byte = TEKRAM_PW|TEKRAM_9600;
break;
case 19200:
byte = TEKRAM_PW|TEKRAM_19200;
break;
case 38400:
byte = TEKRAM_PW|TEKRAM_38400;
break;
case 57600:
byte = TEKRAM_PW|TEKRAM_57600;
break;
case 115200:
byte = TEKRAM_115200;
break;
}
/* Set DTR, Clear RTS */
sirdev_set_dtr_rts(dev, TRUE, FALSE);
/* Wait at least 7us */
udelay(14);
/* Write control byte */
sirdev_raw_write(dev, &byte, 1);
dev->speed = speed;
state = TEKRAM_STATE_WAIT_SPEED;
delay = tekram_delay;
break;
case TEKRAM_STATE_WAIT_SPEED:
/* Set DTR, Set RTS */
sirdev_set_dtr_rts(dev, TRUE, TRUE);
udelay(50);
break;
default:
ERROR("%s - undefined state %d\n", __FUNCTION__, state);
ret = -EINVAL;
break;
}
dev->fsm.substate = state;
return (delay > 0) ? delay : ret;
}
static int tekram_change_speed(struct sir_dev *dev, unsigned speed)
{
unsigned state = dev->fsm.substate;
unsigned delay = 0;
u8 byte;
static int ret = 0;
IRDA_DEBUG(2, "%s()\n", __func__);
switch(state) {
case SIRDEV_STATE_DONGLE_SPEED:
switch (speed) {
default:
speed = 9600;
ret = -EINVAL;
case 9600:
byte = TEKRAM_PW|TEKRAM_9600;
break;
case 19200:
byte = TEKRAM_PW|TEKRAM_19200;
break;
case 38400:
byte = TEKRAM_PW|TEKRAM_38400;
break;
case 57600:
byte = TEKRAM_PW|TEKRAM_57600;
break;
case 115200:
byte = TEKRAM_115200;
break;
}
sirdev_set_dtr_rts(dev, TRUE, FALSE);
udelay(14);
sirdev_raw_write(dev, &byte, 1);
dev->speed = speed;
state = TEKRAM_STATE_WAIT_SPEED;
delay = tekram_delay;
break;
case TEKRAM_STATE_WAIT_SPEED:
sirdev_set_dtr_rts(dev, TRUE, TRUE);
udelay(50);
break;
default:
IRDA_ERROR("%s - undefined state %d\n", __func__, state);
ret = -EINVAL;
break;
}
dev->fsm.substate = state;
return (delay > 0) ? delay : ret;
}
static int mcp2120_change_speed(struct sir_dev *dev, unsigned speed)
{
unsigned state = dev->fsm.substate;
unsigned delay = 0;
u8 control[2];
static int ret = 0;
IRDA_DEBUG(2, "%s()\n", __func__);
switch (state) {
case SIRDEV_STATE_DONGLE_SPEED:
/* Set DTR to enter command mode */
sirdev_set_dtr_rts(dev, TRUE, FALSE);
udelay(500);
ret = 0;
switch (speed) {
default:
speed = 9600;
ret = -EINVAL;
/* fall through */
case 9600:
control[0] = MCP2120_9600;
;
break;
case 19200:
control[0] = MCP2120_19200;
;
break;
case 34800:
control[0] = MCP2120_38400;
;
break;
case 57600:
control[0] = MCP2120_57600;
;
break;
case 115200:
control[0] = MCP2120_115200;
;
break;
}
control[1] = MCP2120_COMMIT;
/* Write control bytes */
sirdev_raw_write(dev, control, 2);
dev->speed = speed;
state = MCP2120_STATE_WAIT_SPEED;
delay = 100;
;
break;
case MCP2120_STATE_WAIT_SPEED:
/* Go back to normal mode */
sirdev_set_dtr_rts(dev, FALSE, FALSE);
;
break;
default:
IRDA_ERROR("%s(), undefine state %d\n", __func__, state);
ret = -EINVAL;
break;
}
dev->fsm.substate = state;
return (delay > 0) ? delay : ret;
}
static int girbil_change_speed(struct sir_dev *dev, unsigned speed)
{
unsigned state = dev->fsm.substate;
unsigned delay = 0;
u8 control[2];
static int ret = 0;
IRDA_DEBUG(2, "%s()\n", __func__);
switch(state) {
case SIRDEV_STATE_DONGLE_SPEED:
sirdev_set_dtr_rts(dev, FALSE, TRUE);
udelay(25);
ret = 0;
switch (speed) {
default:
ret = -EINVAL;
case 9600:
control[0] = GIRBIL_9600;
break;
case 19200:
control[0] = GIRBIL_19200;
break;
case 34800:
control[0] = GIRBIL_38400;
break;
case 57600:
control[0] = GIRBIL_57600;
break;
case 115200:
control[0] = GIRBIL_115200;
break;
}
control[1] = GIRBIL_LOAD;
sirdev_raw_write(dev, control, 2);
dev->speed = speed;
state = GIRBIL_STATE_WAIT_SPEED;
delay = 100;
break;
case GIRBIL_STATE_WAIT_SPEED:
sirdev_set_dtr_rts(dev, TRUE, TRUE);
udelay(25);
break;
default:
IRDA_ERROR("%s - undefined state %d\n", __func__, state);
ret = -EINVAL;
break;
}
dev->fsm.substate = state;
return (delay > 0) ? delay : ret;
}
