static void sm8500_set_info( UINT32 state, cpuinfo *info )
{
switch(state)
{
case CPUINFO_INT_INPUT_STATE + 0:
case CPUINFO_INT_INPUT_STATE + 1:
case CPUINFO_INT_INPUT_STATE + 2:
case CPUINFO_INT_INPUT_STATE + 3:
case CPUINFO_INT_INPUT_STATE + 4:
case CPUINFO_INT_INPUT_STATE + 5:
case CPUINFO_INT_INPUT_STATE + 6:
case CPUINFO_INT_INPUT_STATE + 7:
case CPUINFO_INT_INPUT_STATE + 8:
case CPUINFO_INT_INPUT_STATE + 9:
case CPUINFO_INT_INPUT_STATE + 10:
sm8500_set_irq_line( state - CPUINFO_INT_INPUT_STATE, info->i );
break;
case CPUINFO_INT_REGISTER + SM8500_RR0:
case CPUINFO_INT_REGISTER + SM8500_RR2:
case CPUINFO_INT_REGISTER + SM8500_RR4:
case CPUINFO_INT_REGISTER + SM8500_RR6:
case CPUINFO_INT_REGISTER + SM8500_RR8:
case CPUINFO_INT_REGISTER + SM8500_RR10:
case CPUINFO_INT_REGISTER + SM8500_RR12:
case CPUINFO_INT_REGISTER + SM8500_RR14:
case CPUINFO_INT_REGISTER + SM8500_PC:
case CPUINFO_INT_REGISTER + SM8500_SP:
case CPUINFO_INT_REGISTER + SM8500_PS:
case CPUINFO_INT_REGISTER + SM8500_SYS16:
case CPUINFO_INT_REGISTER + SM8500_SYS:
case CPUINFO_INT_REGISTER + SM8500_IE0:
case CPUINFO_INT_REGISTER + SM8500_IE1:
case CPUINFO_INT_REGISTER + SM8500_IR0:
case CPUINFO_INT_REGISTER + SM8500_IR1:
case CPUINFO_INT_REGISTER + SM8500_P0:
case CPUINFO_INT_REGISTER + SM8500_P1:
case CPUINFO_INT_REGISTER + SM8500_P2:
case CPUINFO_INT_REGISTER + SM8500_P3:
case CPUINFO_INT_REGISTER + SM8500_CKC:
case CPUINFO_INT_REGISTER + SM8500_SPH:
case CPUINFO_INT_REGISTER + SM8500_SPL:
case CPUINFO_INT_REGISTER + SM8500_PS0:
case CPUINFO_INT_REGISTER + SM8500_PS1:
case CPUINFO_INT_REGISTER + SM8500_P0C:
case CPUINFO_INT_REGISTER + SM8500_P1C:
case CPUINFO_INT_REGISTER + SM8500_P2C:
case CPUINFO_INT_REGISTER + SM8500_P3C:
sm8500_set_reg( state - CPUINFO_INT_REGISTER, info->i );
break;
}
}
static void sm8500_set_reg( int regnum, unsigned val )
{
switch( regnum )
{
case REG_PC:
case SM8500_PC: regs.PC = val; break;
case REG_SP:
case SM8500_SP: regs.SP = val; break;
case SM8500_PS: sm8500_set_reg( SM8500_PS0, ( val >> 8 ) & 0xFF ); sm8500_set_reg( SM8500_PS1, val & 0xFF ); break;
case SM8500_SYS16: regs.SYS = val; break;
case SM8500_RR0: sm85cpu_mem_writeword( 0x00, val); break;
case SM8500_RR2: sm85cpu_mem_writeword( 0x02, val); break;
case SM8500_RR4: sm85cpu_mem_writeword( 0x04, val); break;
case SM8500_RR6: sm85cpu_mem_writeword( 0x06, val); break;
case SM8500_RR8: sm85cpu_mem_writeword( 0x08, val); break;
case SM8500_RR10: sm85cpu_mem_writeword( 0x0A, val); break;
case SM8500_RR12: sm85cpu_mem_writeword( 0x0C, val); break;
case SM8500_RR14: sm85cpu_mem_writeword( 0x0E, val); break;
case SM8500_IE0: regs.IE0 = val; break;
case SM8500_IE1: regs.IE1 = val; break;
case SM8500_IR0: regs.IR0 = val; break;
case SM8500_IR1: regs.IR1 = val; break;
case SM8500_P0: regs.P0 = val; break;
case SM8500_P1: regs.P1 = val; break;
case SM8500_P2: regs.P2 = val; break;
case SM8500_P3: regs.P3 = val; break;
case SM8500_SYS: regs.SYS = val; break;
case SM8500_CKC: regs.CKC = val; if ( val & 0x80 ) { regs.clock_changed = 1; }; break;
case SM8500_SPH: regs.SP = ( ( val & 0xFF ) << 8 ) | ( regs.SP & 0xFF ); break;
case SM8500_SPL: regs.SP = ( regs.SP & 0xFF00 ) | ( val & 0xFF ); break;
case SM8500_PS0: regs.PS0 = val; regs.register_base = regs.internal_ram + ( val & 0xF8 ); break;
case SM8500_PS1: regs.PS1 = val; break;
case SM8500_P0C: regs.P0C = val; break;
case SM8500_P1C: regs.P1C = val; break;
case SM8500_P2C: regs.P2C = val; break;
case SM8500_P3C: regs.P3C = val; break;
}
}
