int OVLReset() { unsigned int delay_cnt = 0; static unsigned int cnt=0; printk("[DDP] OVLReset called %d \n", cnt++); DISP_REG_SET(DISP_REG_OVL_RST, 0x1); // soft reset DISP_REG_SET(DISP_REG_OVL_RST, 0x0); while (((DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG)&0x3ff) != 0x1) && ((DISP_REG_GET(DISP_REG_OVL_FLOW_CTRL_DBG)&0x3ff) != 0x2)) { delay_cnt++; if(delay_cnt>10000) { printk("[DDP] error, OVLReset() timeout! \n"); ddp_dump_info(DISP_MODULE_CONFIG); ddp_dump_info(DISP_MODULE_MUTEX); ddp_dump_info(DISP_MODULE_OVL); ddp_dump_info(DISP_MODULE_RDMA); disp_dump_reg(DISP_MODULE_OVL); smi_dumpDebugMsg(); break; } } #if 0 DISP_REG_SET(DISP_REG_OVL_ROI_SIZE , 0x00); // clear regs DISP_REG_SET(DISP_REG_OVL_ROI_BGCLR , 0x00); DISP_REG_SET(DISP_REG_OVL_SRC_CON , 0x00); DISP_REG_SET(DISP_REG_OVL_L0_CON , 0x00); DISP_REG_SET(DISP_REG_OVL_L0_SRCKEY , 0x00); DISP_REG_SET(DISP_REG_OVL_L0_SRC_SIZE , 0x00); DISP_REG_SET(DISP_REG_OVL_L0_OFFSET , 0x00); DISP_REG_SET(DISP_REG_OVL_L0_ADDR , 0x00); DISP_REG_SET(DISP_REG_OVL_L0_PITCH , 0x00); DISP_REG_SET(DISP_REG_OVL_L1_CON , 0x00); DISP_REG_SET(DISP_REG_OVL_L1_SRCKEY , 0x00); DISP_REG_SET(DISP_REG_OVL_L1_SRC_SIZE , 0x00); DISP_REG_SET(DISP_REG_OVL_L1_OFFSET , 0x00); DISP_REG_SET(DISP_REG_OVL_L1_ADDR , 0x00); DISP_REG_SET(DISP_REG_OVL_L1_PITCH , 0x00); DISP_REG_SET(DISP_REG_OVL_L2_CON , 0x00); DISP_REG_SET(DISP_REG_OVL_L2_SRCKEY , 0x00); DISP_REG_SET(DISP_REG_OVL_L2_SRC_SIZE , 0x00); DISP_REG_SET(DISP_REG_OVL_L2_OFFSET , 0x00); DISP_REG_SET(DISP_REG_OVL_L2_ADDR , 0x00); DISP_REG_SET(DISP_REG_OVL_L2_PITCH , 0x00); DISP_REG_SET(DISP_REG_OVL_L3_CON , 0x00); DISP_REG_SET(DISP_REG_OVL_L3_SRCKEY , 0x00); DISP_REG_SET(DISP_REG_OVL_L3_SRC_SIZE , 0x00); DISP_REG_SET(DISP_REG_OVL_L3_OFFSET , 0x00); DISP_REG_SET(DISP_REG_OVL_L3_ADDR , 0x00); DISP_REG_SET(DISP_REG_OVL_L3_PITCH , 0x00); #endif return 0; }
int WDMAReset(unsigned idx) { unsigned int delay_cnt = 0; static unsigned int wdma_timeout_cnt = 0; //WDMA_RST = 0x00; DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_RST , 0x01); // soft reset while((DISP_REG_GET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_FLOW_CTRL_DBG)&0x1) != 0x1) { delay_cnt++; if(delay_cnt>10000) { printk("[DDP] error, WDMAReset(%d) timeout! wdma_timeout_cnt=%d \n", idx, wdma_timeout_cnt++); WDMADumpHidenReg(idx); disp_dump_reg(DISP_MODULE_WDMA0); smi_dumpDebugMsg(); break; } } DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_RST , 0x00); DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_CFG , 0x00); DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_SRC_SIZE , 0x00); DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_CLIP_SIZE , 0x00); DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_CLIP_COORD , 0x00); DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_ADDR , 0x00); DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_DST_W_IN_BYTE , 0x00); DISP_REG_SET(idx*DISP_INDEX_OFFSET+DISP_REG_WDMA_ALPHA , 0x00); // clear regs return 0; }
void _mali_osk_abort(void) { #if 0 int index; /* make a simple fault by dereferencing a NULL pointer */ dump_stack(); for (index = 0; index < 5; index++) { MALI_DEBUG_PRINT(2, ("=== [MALI] PLL Dump %d ===\n", index)); MALI_DEBUG_PRINT(2, ("CLK_CFG_0: 0x%08x\n", *((volatile unsigned int*)CLK_CFG_0))); MALI_DEBUG_PRINT(2, ("VENCPLL_CON0: 0x%08x\n", *((volatile unsigned int*)VENCPLL_CON0))); MALI_DEBUG_PRINT(2, ("MMPLL_CON0: 0x%08x\n", *((volatile unsigned int*)MMPLL_CON0))); MALI_DEBUG_PRINT(2, ("=== [MALI] SMI Dump %d ===\n", index)); smi_dumpDebugMsg(); MALI_DEBUG_PRINT(2, ("=== [MALI] M4U Dump %d ===\n", index)); /// m4u_dump_debug_registers(); } *(int *)0 = 0; #endif // 0 }
int larb_reg_restore(int larb) { unsigned int regval,regval1,regval2; unsigned int larb_base = gLarbBaseAddr[larb]; /* unsigned int* pReg = pLarbRegBackUp[larb]; int i; //warning: larb_con is controlled by set/clr regval = *(pReg++); M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval)); M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval)); M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) ); M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) ); for(i=0; i<3; i++) { M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++)); M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++)); M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++)); } */ //Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns //Got to enable OSTD before engine starts regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT); regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0); regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1); if(0 == regval) { M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff); } else { SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2); smi_dumpDebugMsg(); SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2); } if(0 == g_bInited) { initSetting(); g_bInited = 1; SMIMSG("SMI init\n"); } return 0; }
int larb_reg_restore(int larb) { unsigned int regval,regval1,regval2; unsigned int larb_base = gLarbBaseAddr[larb]; /* unsigned int* pReg = pLarbRegBackUp[larb]; int i; //warning: larb_con is controlled by set/clr regval = *(pReg++); M4U_WriteReg32(larb_base, SMI_LARB_CON_CLR, ~(regval)); M4U_WriteReg32(larb_base, SMI_LARB_CON_SET, (regval)); M4U_WriteReg32(larb_base, SMI_SHARE_EN, *(pReg++) ); M4U_WriteReg32(larb_base, SMI_ROUTE_SEL, *(pReg++) ); for(i=0; i<3; i++) { M4U_WriteReg32(larb_base, SMI_MAU_ENTR_START(i), *(pReg++)); M4U_WriteReg32(larb_base, SMI_MAU_ENTR_END(i), *(pReg++)); M4U_WriteReg32(larb_base, SMI_MAU_ENTR_GID(i), *(pReg++)); } */ //Clock manager enable LARB clock before call back restore already, it will be disabled after restore call back returns //Got to enable OSTD before engine starts regval = M4U_ReadReg32(larb_base , SMI_LARB_STAT); regval1 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ0); regval2 = M4U_ReadReg32(larb_base , SMI_LARB_MON_BUS_REQ1); if(0 == regval) { int retry_count = 0; SMIMSG("Init OSTD for larb_base: 0x%x\n" , larb_base); // Write 0x60 = 0xFFFF_FFFF, enable BW limiter M4U_WriteReg32(larb_base , 0x60 , 0xffffffff); // Polling 0x600 = 0xaaaa for(retry_count= 0; retry_count<64; retry_count++) { if(M4U_ReadReg32(larb_base , 0x600) == 0xaaaa) { //Step3. Once it is found 0x600 == 0xaaaa, we can start to enable outstanding limiter and set outstanding limit break; } SMIMSG("Larb: 0x%x busy : waiting for idle\n" , larb_base); udelay(500); } // Write 0x60 = 0x0, disable BW limiter M4U_WriteReg32(larb_base , 0x60 , 0x0); // enable ISTD M4U_WriteReg32(larb_base , SMI_LARB_OSTD_CTRL_EN , 0xffffffff); } else { SMIMSG("Larb%d is busy : 0x%x , port:0x%x,0x%x ,fail to set OSTD\n" , larb , regval , regval1 , regval2); smi_dumpDebugMsg(); SMIERR("DISP_MDP LARB%d OSTD cannot be set:0x%x,port:0x%x,0x%x\n" , larb , regval , regval1 , regval2); } if(0 == g_bInited) { initSetting(); g_bInited = 1; SMIMSG("SMI init\n"); } // Show SMI always on register when larb 0 is enable if(larb == 0){ SMIMSG("===SMI always on reg dump===\n"); SMIMSG("[0x5C0,0x5C4,0x5C8]=[0x%x,0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C0),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C4),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5C8)); SMIMSG("[0x5CC,0x5D0]=[0x%x,0x%x]\n" ,M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5CC),M4U_ReadReg32(SMI_COMMON_AO_BASE , 0x5D0)); } return 0; }