static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
/* Builtin devices on Bus 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
/* Firewire 4:0.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
// riser slot top 5:8.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
// riser slot middle 5:9.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
// riser slot bottom 5:a.0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
/* Onboard Ethernet */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
int ioapic_id, ioapic_ver, isa_bus;
struct mp_config_table *mc;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
ioapic_id = 2;
ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */
smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR);
/* Legacy Interrupts */
mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
/* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13);
/* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0, MP_APIC_ALL, 0x1);
/* Compute the checksums. */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int i, bus_isa;
struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
m = sysconf.mb;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev = 0;
struct resource *res;
for(i=0; i<3; i++) {
dev = dev_find_device(0x1166, 0x0235, dev);
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
}
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
//IDE
outb(0x02, 0xc00); outb(0x0e, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe); // IDE
//SATA
outb(0x07, 0xc00); outb(0x0f, 0xc01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xf);
//USB
outb(0x01, 0xc00); outb(0x0a, 0xc01);
for(i=0;i<3;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, m->apicid_bcm5785[0], 0xa); //
}
/* enable int */
/* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
{
device_t dev;
dev = dev_find_device(0x1166, 0x0205, 0);
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
dword |= (1<<4); // enable interrupts
pci_write_config32(dev, 0x6c, dword);
}
}
//First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
// AIC 8130 Galileo Technology...
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (6<<2)|i, m->apicid_bcm5785[1], 2 + (1+i)%4); //
}
//pci slot (on bcm5785)
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (5<<2)|i, m->apicid_bcm5785[1], 8+i%4); //
}
//onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (4<<2)|0, m->apicid_bcm5785[1], 0x1);
//PCI-X on bcm5780
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[1], (4<<2)|i, m->apicid_bcm5785[1], 2 + (0+i)%4); //
}
//onboard Broadcom
for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[2], (4<<2)|i, m->apicid_bcm5785[1], 0xa + (0+i)%4); //
}
// First PCI-E x8
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0<<2)|i, m->apicid_bcm5785[1], 0xe); //
}
// Second PCI-E x8
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[3], (0<<2)|i, m->apicid_bcm5785[1], 0xc); //
}
// Third PCI-E x1
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[4], (0<<2)|i, m->apicid_bcm5785[1], 0xd); //
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
//
// The commented-out lines are auto-detected on my servers.
//
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
// Integrated SMBus 2.0
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
// Integrated AMD AC97 Audio
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
// Integrated AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13);
// On board ATI Rage XL
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
// On board Broadcom nics
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
// On board LSI SCSI
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
// PCIX-133 Slot
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
{
device_t dev;
struct resource *res;
dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 3, 0x20, res->base);
}
}
dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 4, 0x20, res->base);
}
}
dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 5, 0x20, res->base);
}
}
dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 8, 0x20, res->base);
}
}
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x0, 0x1, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x1, 0x1, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x0, 0x1, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x3, 0x1, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x4, 0x1, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x6, 0x1, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x7, 0x1, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x1, 0x8, 0x1, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0x9, 0x1, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xc, 0x1, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xd, 0x1, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x1, 0xe, 0x1, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x1, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x1, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x1, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x1, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x1, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x1, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x78, 0x1, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x79, 0x1, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7a, 0x1, 0x12);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LOCAL_APIC_ADDR);
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 0x2, 0x20, 0xfec00000);
mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x3, 0x0,
0x2, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0x1, 0x2, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0x0, 0x2, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0x3, 0x2, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0x4, 0x2, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0x5, 0x2, 0x5);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0x6, 0x2, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0x7, 0x2, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0x8, 0x2, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0x9, 0x2, 0x9);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0xa, 0x2, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0xb, 0x2, 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0xc, 0x2, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0xd, 0x2, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0xe, 0x2, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
0x3, 0xf, 0x2, 0xf);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_lintsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x3, 0x0,
MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI,
MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x3, 0x0,
MP_APIC_ALL, 0x1);
return mptable_finalize(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
}
/* Initialize interrupt mapping*/
dword = 0x0120d218;
pci_write_config32(dev, 0x7c, dword);
dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d;
pci_write_config32(dev, 0x84, dword);
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
}
}
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
// Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
// Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
// Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
// Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
// Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
//Slot PCIE x16
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
}
//Slot PCIE x4
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
}
//Onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19
//Channel B of 8131
//Onboard Broadcom NIC
for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
}
//Channel A of 8131
//Slot 4 PCIX 133/100/66
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24
}
//Slot 3 PCIX 133/100/66 SoDIMM PCI
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";
static const char productid[12] = "E325 ";
struct mp_config_table *mc;
unsigned char bus_num;
unsigned char bus_isa;
unsigned char bus_8111_0;
unsigned char bus_8111_1;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
{
device_t dev;
/* 8111 */
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_0 = 1;
bus_8111_1 = 4;
bus_isa = 5;
}
/* 8131-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
bus_8131_1 = 2;
}
/* 8131-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8131_2 = 3;
}
}
/* define bus and isa numbers */
for (bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
/* Legacy IOAPIC #2 */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
{
device_t dev;
struct resource *res;
/* 8131-1 apic #3 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x11, res->base);
}
}
/* 8131-2 apic #4 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x11, res->base);
}
}
}
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
/* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
/* Integrated SMBus 2.0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
/* Integrated AMD AC97 Audio */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
/* Integrated AMD USB */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
/* On board ATI Rage XL */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
/* On board Broadcom nics */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
/* On board LSI SCSI */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
/* PCI Slot 1 PCIX */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
/* PCI Slot 2 PCIX */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
/* Standard local interrupt assignments:
* Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_pxhd_3;
unsigned char bus_pxhd_4;
unsigned char bus_ich5r_1;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
{
device_t dev;
/* ich5r */
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
bus_ich5r_1 = 7;
}
/* pxhd-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
if (dev) {
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
bus_pxhd_1 = 2;
}
/* pxhd-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
if (dev) {
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
bus_pxhd_2 = 3;
}
/* pxhd-3 */
dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
if (dev) {
bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
bus_pxhd_3 = 5;
}
/* pxhd-4 */
dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
if (dev) {
bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
bus_pxhd_4 = 6;
}
}
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
{
struct resource *res;
device_t dev;
/* pxhd apic 3 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x03, 0x20, res->base);
}
}
else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
}
/* pxhd apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x20, res->base);
}
}
else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
}
}
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
/* ISA backward compatibility interrupts */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x74, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x76, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x77, 0x02, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x75, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x74, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x7c, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x7d, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pxhd_1, 0x08, 0x03, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pxhd_1, 0x0c, 0x03, 0x06);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pxhd_1, 0x0d, 0x03, 0x07);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pxhd_2, 0x08, 0x04, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_ich5r_1, 0x04, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
bus_pxhd_4, 0x00, 0x02, 0x10);
#if 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
(bus_isa - 1), 0x04, 0x02, 0x10);
#endif
/* Standard local interrupt assignments */
#if 0
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x00, MP_APIC_ALL, 0x00);
#endif
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x00, MP_APIC_ALL, 0x01);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
get_bus_conf();
sbdn = sysconf.sbdn;
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
device_t dev;
struct resource *res;
uint32_t dword;
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11,
res->base);
}
/* Initialize interrupt mapping. */
dword = 0x01200000;
pci_write_config32(dev, 0x7c, dword);
dword = 0x12008009;
pci_write_config32(dev, 0x80, dword);
dword = 0x0002010d;
pci_write_config32(dev, 0x84, dword);
}
}
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
// Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
0xa);
// Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
0x15);
// Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
0x14);
// Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
0x17);
// Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
0x16);
// Onboard ck804 NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804,
0x17);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_lintsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_ck804[0], 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
bus_ck804[0], 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums. */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";
static const char productid[12] = "Truxton ";
struct mp_config_table *mc;
u8 bus_num;
u8 bus_isa;
u8 bus_pea0 = 0;
u8 bus_pea1 = 0;
u8 bus_aioc;
device_t dev;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
/* AIOC bridge */
dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
if (dev) {
bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
bus_aioc = 0;
bus_isa = 9;
}
/* PCIe A0 */
dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
if (dev) {
bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
bus_pea0 = 0;
}
/* PCIe A1 */
dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
if (dev) {
bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
bus_pea1 = 0;
}
/* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI ");
}
smp_write_bus(mc, bus_isa, "ISA ");
/* IOAPIC handling */
smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
/* Standard local interrupt assignments */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, MP_APIC_ALL, 0x00);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, MP_APIC_ALL, 0x01);
/* IMCH/IICH PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
if (bus_pea0) {
/* PCIe slot 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|0, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|1, 0x8, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|2, 0x8, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|3, 0x8, 0x13);
}
if (bus_pea1) {
/* PCIe slots 1-4 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|0, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|1, 0x8, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|2, 0x8, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|3, 0x8, 0x13);
}
if (bus_aioc) {
/* AIOC PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
}
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
u8 bus_pea0 = 0;
u8 bus_pea1 = 0;
u8 bus_aioc;
device_t dev;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
/* AIOC bridge */
dev = dev_find_slot(0, PCI_DEVFN(0x04,0));
if (dev) {
bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n");
bus_aioc = 0;
}
/* PCIe A0 */
dev = dev_find_slot(0, PCI_DEVFN(0x02,0));
if (dev) {
bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n");
bus_pea0 = 0;
}
/* PCIe A1 */
dev = dev_find_slot(0, PCI_DEVFN(0x03,0));
if (dev) {
bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n");
bus_pea1 = 0;
}
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);
/* Standard local interrupt assignments */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, MP_APIC_ALL, 0x00);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_isa, 0x00, MP_APIC_ALL, 0x01);
/* IMCH/IICH PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */
if (bus_pea0) {
/* PCIe slot 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|0, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|1, 0x8, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|2, 0x8, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea0, (0<<2)|3, 0x8, 0x13);
}
if (bus_pea1) {
/* PCIe slots 1-4 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|0, 0x8, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|1, 0x8, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|2, 0x8, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_pea1, (0<<2)|3, 0x8, 0x13);
}
if (bus_aioc) {
/* AIOC PCI devices */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */
}
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_esb6300_1;
unsigned char bus_esb6300_2;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc);
{
device_t dev;
/* esb6300_2 */
dev = dev_find_slot(0, PCI_DEVFN(0x1c,0));
if (dev) {
bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n");
bus_esb6300_1 = 6;
}
/* esb6300_1 */
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
bus_esb6300_2 = 7;
}
/* pxhd-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
if (dev) {
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n");
bus_pxhd_1 = 2;
}
/* pxhd-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
if (dev) {
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
bus_pxhd_2 = 3;
}
}
mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
smp_write_ioapic(mc, 3, 0x20, IO_APIC_ADDR + 0x10000);
{
struct resource *res;
device_t dev;
/* PXHd apic 4 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x04, 0x20, res->base);
}
} else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
}
/* PXHd apic 5 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, 0x05, 0x20, res->base);
}
} else {
printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev);
}
}
mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x74, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x77, 0x02, 0x17);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x75, 0x02, 0x13);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x7c, 0x02, 0x12);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
0x00, 0x7d, 0x02, 0x11);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
0x03, 0x08, 0x05, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
0x03, 0x08, 0x05, 0x04);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
bus_esb6300_1, 0x04, 0x03, 0x00);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
bus_esb6300_1, 0x08, 0x03, 0x01);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
bus_esb6300_2, 0x04, 0x02, 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, // -- added
bus_esb6300_2, 0x08, 0x02, 0x14);
/* Standard local interrupt assignments */
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x00, MP_APIC_ALL, 0x00);
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
bus_isa, 0x00, MP_APIC_ALL, 0x01);
/* FIXME verify I have the irqs handled for all of the risers */
/* Compute the checksums */
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
static void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
static const char oem[8] = "COREBOOT";
static const char productid[12] = "PC2500 ";
struct mp_config_table *mc;
int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0;
mc->mpe_checksum = 0;
mc->reserved = 0;
smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR);
/* Now, assemble the table. */
mptable_add_isa_interrupts(mc, isa_bus, VT8237R_APIC_ID, 0);
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, \
bus, (((dev)<<2)|(fn)), VT8237R_APIC_ID, (pin))
// PCI slot 1
PCI_INT(0, 8, 0, 16);
PCI_INT(0, 8, 1, 17);
PCI_INT(0, 8, 2, 18);
PCI_INT(0, 8, 3, 19);
// PCI slot 2
PCI_INT(0, 9, 0, 17);
PCI_INT(0, 9, 1, 18);
PCI_INT(0, 9, 2, 19);
PCI_INT(0, 9, 3, 16);
// SATA
PCI_INT(0, 15, 1, 20);
// USB
PCI_INT(0, 16, 0, 21);
PCI_INT(0, 16, 1, 21);
PCI_INT(0, 16, 2, 21);
PCI_INT(0, 16, 3, 21);
// Audio
PCI_INT(0, 17, 2, 22);
// Ethernet
PCI_INT(0, 18, 0, 23);
/* Onboard VGA */
PCI_INT(1, 0, 0, 16);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_lintsrc(mc, mp_ExtINT,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
0, 0x0, MP_APIC_ALL, 0x0);
smp_write_lintsrc(mc, mp_NMI,
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
0, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
mc->mpe_checksum =
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc);
}
