static int tegra_voice_call_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_codec *codec = rtd->codec; struct snd_soc_card *card = codec->card; struct tegra_max98088 *machine = snd_soc_card_get_drvdata(card); int srate, mclk; int err; srate = params_rate(params); switch (srate) { case 8000: case 16000: case 24000: case 32000: case 48000: case 64000: case 96000: mclk = 12288000; break; case 11025: case 22050: case 44100: case 88200: mclk = 11289600; break; default: return -EINVAL; break; } err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk); if (err < 0) { if (!(machine->util_data.set_mclk % mclk)) mclk = machine->util_data.set_mclk; else { dev_err(card->dev, "Can't configure clocks\n"); return err; } } tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1); err = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (err < 0) { dev_err(card->dev, "codec_dai fmt not set\n"); return err; } err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk, SND_SOC_CLOCK_IN); if (err < 0) { dev_err(card->dev, "codec_dai clock not set\n"); return err; } #ifndef CONFIG_ARCH_TEGRA_2x_SOC /* codec configuration */ machine->codec_info[HIFI_CODEC].rate = params_rate(params); machine->codec_info[HIFI_CODEC].channels = params_channels(params); machine->codec_info[HIFI_CODEC].bitsize = 16; machine->codec_info[HIFI_CODEC].is_i2smaster = 1; machine->codec_info[HIFI_CODEC].is_format_dsp = 0; /* baseband configuration */ machine->codec_info[BASEBAND].bitsize = 16; machine->codec_info[BASEBAND].is_i2smaster = 1; machine->codec_info[BASEBAND].is_format_dsp = 1; #endif machine->is_device_bt = 0; return 0; }
static int imx_3stack_surround_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_dai *codec_dai = rtd->codec_dai; unsigned int rate = params_rate(params); u32 dai_format; unsigned int lrclk_ratio = 0; if (hw_state.hw) return 0; hw_state.hw = 1; if (cpu_is_mx53()) { switch (rate) { case 32000: lrclk_ratio = 3; break; case 48000: lrclk_ratio = 3; break; case 64000: lrclk_ratio = 1; break; case 96000: lrclk_ratio = 1; break; case 128000: lrclk_ratio = 1; break; case 44100: lrclk_ratio = 3; break; case 88200: lrclk_ratio = 1; break; case 176400: lrclk_ratio = 0; break; case 192000: lrclk_ratio = 0; break; default: pr_info("Rate not support.\n"); return -EINVAL;; } } else if (cpu_is_mx6q()) { switch (rate) { case 32000: lrclk_ratio = 5; break; case 48000: lrclk_ratio = 5; break; case 64000: lrclk_ratio = 2; break; case 96000: lrclk_ratio = 2; break; case 128000: lrclk_ratio = 2; break; case 44100: lrclk_ratio = 5; break; case 88200: lrclk_ratio = 2; break; case 176400: lrclk_ratio = 0; break; case 192000: lrclk_ratio = 0; break; default: pr_info("Rate not support.\n"); return -EINVAL;; } } dai_format = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS; /* set cpu DAI configuration */ snd_soc_dai_set_fmt(cpu_dai, dai_format); /* set i.MX active slot mask */ snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 2, 32); /* set the ESAI system clock as output */ if (cpu_is_mx53()) { snd_soc_dai_set_sysclk(cpu_dai, ESAI_CLK_EXTAL, mclk_freq, SND_SOC_CLOCK_OUT); } else if (cpu_is_mx6q()) { snd_soc_dai_set_sysclk(cpu_dai, ESAI_CLK_EXTAL_DIV, mclk_freq, SND_SOC_CLOCK_OUT); } /* set the ratio */ snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PSR, 1); if (cpu_is_mx53()) snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PM, 0); else if (cpu_is_mx6q()) snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PM, 2); snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_FP, lrclk_ratio); snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PSR, 1); if (cpu_is_mx53()) snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PM, 0); else if (cpu_is_mx6q()) snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PM, 2); snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_FP, lrclk_ratio); /* set codec DAI configuration */ snd_soc_dai_set_fmt(codec_dai, dai_format); /* set codec Master clock */ snd_soc_dai_set_sysclk(codec_dai, 0, mclk_freq, SND_SOC_CLOCK_IN); return 0; }
static int smdk_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_dai *codec_dai = rtd->codec_dai; unsigned int pll_out; int bfs, rfs, ret; switch (params_format(params)) { case SNDRV_PCM_FORMAT_U8: case SNDRV_PCM_FORMAT_S8: bfs = 16; break; case SNDRV_PCM_FORMAT_U16_LE: case SNDRV_PCM_FORMAT_S16_LE: bfs = 32; break; default: return -EINVAL; } /* The Fvco for WM8580 PLLs must fall within [90,100]MHz. * This criterion can't be met if we request PLL output * as {8000x256, 64000x256, 11025x256}Hz. * As a wayout, we rather change rfs to a minimum value that * results in (params_rate(params) * rfs), and itself, acceptable * to both - the CODEC and the CPU. */ switch (params_rate(params)) { case 16000: case 22050: case 32000: case 44100: case 48000: case 88200: case 96000: rfs = 256; break; case 64000: rfs = 384; break; case 8000: case 11025: rfs = 512; break; default: return -EINVAL; } pll_out = params_rate(params) * rfs; /* Set the Codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; /* Set the AP DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; /* Set WM8580 to drive MCLK from its PLLA */ ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK, WM8580_CLKSRC_PLLA); if (ret < 0) return ret; ret = snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 0, SMDK_WM8580_FREQ, pll_out); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(codec_dai, WM8580_CLKSRC_PLLA, pll_out, SND_SOC_CLOCK_IN); if (ret < 0) return ret; return 0; }
static int sunxi_snddaudio1_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { int ret = 0; u32 freq_in = 24000000; u32 freq_out = 22579200; struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned long sample_rate = params_rate(params); switch (sample_rate) { case 8000: case 16000: case 32000: case 64000: case 128000: case 12000: case 24000: case 48000: case 96000: case 192000: freq_out = 24576000; break; } /* set the codec FLL */ ret = snd_soc_dai_set_pll(codec_dai, AC100_MCLK1, 0, freq_in, freq_out); if (ret < 0) { return ret; } /*set system clock source freq and set the mode as daudio or pcm*/ ret = snd_soc_dai_set_sysclk(cpu_dai, 0 , freq_out, daudio_pcm_select); if (ret < 0) { return ret; } ret = codec_dai->driver->ops->set_sysclk(codec_dai, AIF1_CLK, freq_out, SND_SOC_CLOCK_IN); if (ret < 0) return ret; ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) { pr_err("%s, line:%d\n", __func__, __LINE__); return ret; } /* * codec clk & FRM master. AP as slave */ ret = snd_soc_dai_set_fmt(cpu_dai, (audio_format | (signal_inversion<<8) | (daudio_master<<12))); if (ret < 0) { return ret; } ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, sample_rate); if (ret < 0) { return ret; } /* * audio_format == SND_SOC_DAIFMT_DSP_A * signal_inversion<<8 == SND_SOC_DAIFMT_IB_NF * daudio_master<<12 == SND_SOC_DAIFMT_CBM_CFM */ DAUDIO_DBG("%s,line:%d,audio_format:%d,SND_SOC_DAIFMT_DSP_A:%d\n",\ __func__, __LINE__, audio_format, SND_SOC_DAIFMT_DSP_A); DAUDIO_DBG("%s,line:%d,signal_inversion:%d,signal_inversion<<8:%d,SND_SOC_DAIFMT_IB_NF:%d\n",\ __func__, __LINE__, signal_inversion, signal_inversion<<8, SND_SOC_DAIFMT_IB_NF); DAUDIO_DBG("%s,line:%d,daudio_master:%d,daudio_master<<12:%d,SND_SOC_DAIFMT_CBM_CFM:%d\n",\ __func__, __LINE__, daudio_master, daudio_master<<12, SND_SOC_DAIFMT_CBM_CFM); return 0; }
static int midas_wm1811_aif2_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; int ret; int prate; int bclk; dev_info(codec_dai->dev, "%s ++\n", __func__); prate = params_rate(params); switch (params_rate(params)) { case 8000: case 16000: break; default: dev_warn(codec_dai->dev, "Unsupported LRCLK %d, falling back to 8000Hz\n", (int)params_rate(params)); prate = 8000; } #if defined(CONFIG_LTE_MODEM_CMC221) || defined(CONFIG_MACH_M0_CTC) #if defined(CONFIG_MACH_C1_KOR_LGT) || defined(CONFIG_MACH_BAFFIN_KOR_LGT) /* Set the codec DAI configuration */ if (aif2_mode == 0) { if (kpcs_mode == 1) ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); else ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS); } else ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); #else if (aif2_mode == 0) /* Set the codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS); else ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM); #endif #else /* Set the codec DAI configuration, aif2_mode:0 is slave */ if (aif2_mode == 0) ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); else ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); #endif if (ret < 0) return ret; #if defined(CONFIG_LTE_MODEM_CMC221) if (kpcs_mode == 1) { switch (prate) { case 8000: bclk = 256000; break; case 16000: bclk = 512000; break; default: return -EINVAL; } } else { bclk = 2048000; } #elif defined(CONFIG_MACH_M0_CTC) bclk = 2048000; #else switch (prate) { case 8000: bclk = 256000; break; case 16000: bclk = 512000; break; default: return -EINVAL; } #endif #ifdef SND_USE_BIAS_LEVEL if (!midas_fll1_active) midas_start_fll1(midas_aif1_dai); #endif if (aif2_mode == 0) { ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL2, WM8994_FLL_SRC_BCLK, bclk, prate * 256); } else { ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL2, WM8994_FLL_SRC_MCLK1, MIDAS_DEFAULT_MCLK1, prate * 256); } if (ret < 0) dev_err(codec_dai->dev, "Unable to configure FLL2: %d\n", ret); ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL2, prate * 256, SND_SOC_CLOCK_IN); if (ret < 0) dev_err(codec_dai->dev, "Unable to switch to FLL2: %d\n", ret); dev_info(codec_dai->dev, "%s --\n", __func__); return 0; }
/* XXX RFS & SRC_CLK --> Prescalar Value(SRC_CLK / RFS_VAL / fs - 1) XXX */ static int smdkc100_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; int bfs, rfs, psr, ret; #if 1 writel(readl(S5P_CLKGATE_D20)|S5P_CLKGATE_D20_HCLKD2|S5P_CLKGATE_D20_I2SD2,S5P_CLKGATE_D20); writel(readl(S5P_LPMP_MODE_SEL) | (1<<1), S5P_LPMP_MODE_SEL); #endif /* Choose BFS and RFS values combination that is supported by * both the S5M8751 codec as well as the S5PC100 AP * * S5M8751 codec supports only S16_LE, S18_3LE, S20_3LE & S24_LE. * S5PC100 AP supports only S8, S16_LE & S24_LE. * We implement all for completeness but only S16_LE & S24_LE bit-lengths * are possible for this AP-Codec combination. */ switch (params_format(params)) { case SNDRV_PCM_FORMAT_S8: bfs = 16; rfs = 256; /* Can take any RFS value for AP */ break; case SNDRV_PCM_FORMAT_S16_LE: bfs = 32; rfs = 256; /* Can take any RFS value for AP */ break; case SNDRV_PCM_FORMAT_S18_3LE: case SNDRV_PCM_FORMAT_S20_3LE: case SNDRV_PCM_FORMAT_S24_LE: bfs = 48; rfs = 512; /* B'coz 48-BFS needs atleast 512-RFS acc to *S5P6440* UserManual */ /* And S5P6440 uses the same I2S IP as S3C */ break; default: return -EINVAL; } /* Select the AP Sysclk */ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_CDCLKSRC_INT, params_rate(params), SND_SOC_CLOCK_OUT); if (ret < 0) return ret; #ifdef USE_CLKAUDIO ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_CLKSRC_CLKAUDIO, params_rate(params), SND_SOC_CLOCK_OUT); #else ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_CLKSRC_PCLK, 0, SND_SOC_CLOCK_OUT); #endif if (ret < 0) return ret; /* Set the AP DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; /* Set the AP RFS */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_DIV_MCLK, rfs); if (ret < 0) return ret; /* Set the AP BFS */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_DIV_BCLK, bfs); if (ret < 0) return ret; switch (params_rate(params)) { case 8000: case 11025: case 16000: case 22050: case 32000: case 44100: case 48000: case 64000: case 88200: case 96000: psr = SRC_CLK / rfs / params_rate(params); ret = SRC_CLK / rfs - psr * params_rate(params); if(ret >= params_rate(params)/2) // round off psr += 1; psr -= 1; break; default: return -EINVAL; } //printk("SRC_CLK=%d PSR=%d RFS=%d BFS=%d\n", SRC_CLK, psr, rfs, bfs); /* Set the AP Prescalar */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_DIV_PRESCALER, psr); if (ret < 0) return ret; /* Set the Codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; /* Set the Codec BCLK(no option to set the MCLK) */ ret = snd_soc_dai_set_clkdiv(codec_dai, S5M8751_BCLK, bfs); if (ret < 0) return ret; return 0; }
static int midas_wm1811_aif2_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; int ret; int prate; int bclk; prate = params_rate(params); switch (params_rate(params)) { case 8000: case 16000: break; default: dev_warn(codec_dai->dev, "Unsupported LRCLK %d, falling back to 8000Hz\n", (int)params_rate(params)); prate = 8000; } #ifdef CONFIG_LTE_MODEM_CMC221 /* Set the codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS); #else /* Set the codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); #endif if (ret < 0) return ret; #ifdef CONFIG_LTE_MODEM_CMC221 bclk = 2048000; #else switch (prate) { case 8000: bclk = 256000; break; case 16000: bclk = 512000; break; default: return -EINVAL; } #endif ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL2, WM8994_FLL_SRC_BCLK, bclk, prate * 256); if (ret < 0) dev_err(codec_dai->dev, "Unable to configure FLL2: %d\n", ret); ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL2, prate * 256, SND_SOC_CLOCK_IN); if (ret < 0) dev_err(codec_dai->dev, "Unable to switch to FLL2: %d\n", ret); return 0; }
static int rk29_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned int pll_out = 0; unsigned int lrclk = 0; int ret; DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); /*by Vincent Hsiung for EQ Vol Change*/ #define HW_PARAMS_FLAG_EQVOL_ON 0x21 #define HW_PARAMS_FLAG_EQVOL_OFF 0x22 if ((params->flags == HW_PARAMS_FLAG_EQVOL_ON)||(params->flags == HW_PARAMS_FLAG_EQVOL_OFF)) { ret = codec_dai->driver->ops->hw_params(substream, params, codec_dai); //by Vincent DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); } else { /* set codec DAI configuration */ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE) ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); #endif #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER) ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM ); #endif if (ret < 0) return ret; /* set cpu DAI configuration */ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE) ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); #endif #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER) ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); #endif if (ret < 0) return ret; } switch(params_rate(params)) { case 8000: case 16000: case 24000: case 32000: case 48000: pll_out = 12288000; break; case 11025: case 22050: case 44100: pll_out = 11289600; break; default: DBG("Enter:%s, %d, Error rate=%d\n",__FUNCTION__,__LINE__,params_rate(params)); return -EINVAL; break; } DBG("Enter:%s, %d, rate=%d\n",__FUNCTION__,__LINE__,params_rate(params)); #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE) #if 0 //use pll from blck /*Set the pll of rt5633,the Pll source from BITCLK on CPU is master mode*/ //bitclk is 64fs ret=snd_soc_dai_set_pll(codec_dai,0,params_rate(params)*64,pll_out); if (ret < 0) { DBG("rk29_hw_params_rt5633:failed to set the pll for codec side\n"); return ret; } #endif /*Set the system clk for codec*/ ret=snd_soc_dai_set_sysclk(codec_dai, 0,pll_out,SND_SOC_CLOCK_IN); if (ret < 0) { DBG("rk29_hw_params_rt5633:failed to set the sysclk for codec side\n"); return ret; } #endif /* #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER) if((24576000%params_rate(params))==0) //for 8k,16k,32k,48k { snd_soc_dai_set_pll(codec_dai,0,pll_out, 24576000); snd_soc_dai_set_sysclk(codec_dai,0, 24576000, SND_SOC_CLOCK_IN); } else if((22579200%params_rate(params))==0) //for 11k,22k,44k { snd_soc_dai_set_pll(codec_dai,0,pll_out, 22579200); snd_soc_dai_set_sysclk(codec_dai,0, 22579200, SND_SOC_CLOCK_IN); } #endif */ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE) snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, (pll_out/4)/params_rate(params)-1); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3); #endif DBG("Enter:%s, %d, LRCK=%d\n",__FUNCTION__,__LINE__,(pll_out/4)/params_rate(params)); return 0; }
static int tab3_wm1811_aif2_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_codec *codec = rtd->codec; struct snd_soc_dai *codec_dai = rtd->codec_dai; int ret; int prate; int bclk; dev_info(codec_dai->dev, "%s ++\n", __func__); prate = params_rate(params); switch (params_rate(params)) { case 8000: case 16000: break; default: dev_warn(codec_dai->dev, "Unsupported LRCLK %d, falling back to 8000Hz\n", (int)params_rate(params)); prate = 8000; } /* Set the codec DAI configuration, aif2_mode:0 is slave */ if (aif2_mode == 0) ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); else ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; switch (prate) { case 8000: bclk = 256000; break; case 16000: bclk = 512000; break; default: return -EINVAL; } if (aif2_mode == 0) { ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL2, WM8994_FLL_SRC_BCLK, bclk, prate * 256); } else { ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL2, WM8994_FLL_SRC_MCLK1, MIDAS_DEFAULT_MCLK1, prate * 256); } if (ret < 0) dev_err(codec_dai->dev, "Unable to configure FLL2: %d\n", ret); ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL2, prate * 256, SND_SOC_CLOCK_IN); if (ret < 0) dev_err(codec_dai->dev, "Unable to switch to FLL2: %d\n", ret); dev_info(codec_dai->dev, "%s --\n", __func__); return 0; }
static int sunxi_sndi2s1_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { int ret = 0; u32 freq = 22579200; struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned long sample_rate = params_rate(params); switch (sample_rate) { case 8000: case 16000: case 32000: case 64000: case 128000: case 12000: case 24000: case 48000: case 96000: case 192000: freq = 24576000; break; } /*set system clock source freq and set the mode as i2s1 or pcm*/ ret = snd_soc_dai_set_sysclk(cpu_dai, 0 , freq, i2s1_pcm_select); if (ret < 0) { return ret; } ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) return ret; /* * codec clk & FRM master. AP as slave */ ret = snd_soc_dai_set_fmt(cpu_dai, (audio_format | (signal_inversion<<8) | (i2s1_master<<12))); if (ret < 0) { return ret; } ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, sample_rate); if (ret < 0) { return ret; } /* * audio_format == SND_SOC_DAIFMT_DSP_A * signal_inversion<<8 == SND_SOC_DAIFMT_IB_NF * i2s1_master<<12 == SND_SOC_DAIFMT_CBM_CFM */ I2S1_DBG("%s,line:%d,audio_format:%d,SND_SOC_DAIFMT_DSP_A:%d\n",\ __func__, __LINE__, audio_format, SND_SOC_DAIFMT_DSP_A); I2S1_DBG("%s,line:%d,signal_inversion:%d,signal_inversion<<8:%d,SND_SOC_DAIFMT_IB_NF:%d\n",\ __func__, __LINE__, signal_inversion, signal_inversion<<8, SND_SOC_DAIFMT_IB_NF); I2S1_DBG("%s,line:%d,i2s1_master:%d,i2s1_master<<12:%d,SND_SOC_DAIFMT_CBM_CFM:%d\n",\ __func__, __LINE__, i2s1_master, i2s1_master<<12, SND_SOC_DAIFMT_CBM_CFM); return 0; }
static int tegra_hifi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; struct snd_soc_codec *codec = codec_dai->codec; struct tegra_audio_data* audio_data = rtd->socdev->codec_data; enum dac_dap_data_format data_fmt; int dai_flag = 0, sys_clk; int err; ASOC_FUNCTION(""); if (tegra_das_is_port_master(tegra_audio_codec_type_hifi)) dai_flag |= SND_SOC_DAIFMT_CBM_CFM; else dai_flag |= SND_SOC_DAIFMT_CBS_CFS; data_fmt = tegra_das_get_codec_data_fmt(tegra_audio_codec_type_hifi); /* We are supporting DSP and I2s format for now */ if (data_fmt & dac_dap_data_format_i2s) dai_flag |= SND_SOC_DAIFMT_I2S; else dai_flag |= SND_SOC_DAIFMT_DSP_A; err = snd_soc_dai_set_fmt(codec_dai, dai_flag); if (err < 0) { pr_err("codec_dai fmt not set \n"); return err; } err = snd_soc_dai_set_fmt(cpu_dai, dai_flag); if (err < 0) { pr_err("cpu_dai fmt not set \n"); return err; } sys_clk = clk_get_rate(audio_data->dap_mclk); err = snd_soc_dai_set_sysclk(codec_dai, 0, sys_clk, SND_SOC_CLOCK_IN); if (err < 0) { pr_err("codec_dai clock not set\n"); return err; } err = snd_soc_dai_set_sysclk(cpu_dai, 0, sys_clk, SND_SOC_CLOCK_IN); if (err < 0) { pr_err("cpu_dai clock not set\n"); return err; } if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) { int CtrlReg = 0; int VolumeCtrlReg = 0; int SidetoneCtrlReg = 0; int SideToneAtenuation = 0; snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0, 0X7); snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0, 0X7); /* Mic Bias enable */ CtrlReg = (0x1<<B00_MICBIAS_ENA) | (0x1<<B01_MICDET_ENA); snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, CtrlReg); /* Enable DRC */ CtrlReg = snd_soc_read(codec, WM8903_DRC_0); CtrlReg |= (1<<B15_DRC_ENA); snd_soc_write(codec, WM8903_DRC_0, CtrlReg); CtrlReg = LUNA_INTERNAL_MIC_SETTING_R1R2; snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_1, CtrlReg); CtrlReg = LUNA_EXTERNAL_MIC_SETTING_L2L1; snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_1, CtrlReg); VolumeCtrlReg = (0x1C << B00_IN_VOL); /* Mic Setting */ snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0, VolumeCtrlReg); snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0, VolumeCtrlReg); CtrlReg = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_0); CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCR, 0x0); CtrlReg = SET_REG_VAL(CtrlReg, 0x1, B07_AIF_ADCL, 0x0); snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg); /* Enable analog inputs */ CtrlReg = (0x1<<B01_INL_ENA) | (0x1<<B00_INR_ENA); snd_soc_write(codec, WM8903_POWER_MANAGEMENT_0, CtrlReg); /* ADC Settings */ CtrlReg = snd_soc_read(codec, WM8903_ADC_DIGITAL_0); CtrlReg |= (0x1<<B04_ADC_HPF_ENA); snd_soc_write(codec, WM8903_ADC_DIGITAL_0, CtrlReg); #if 0 SidetoneCtrlReg = 0; snd_soc_write(codec, R20_SIDETONE_CTRL, SidetoneCtrlReg); #endif /* Enable ADC */ CtrlReg = snd_soc_read(codec, WM8903_POWER_MANAGEMENT_6); CtrlReg |= (0x1<<B00_ADCR_ENA)|(0x1<<B01_ADCL_ENA); snd_soc_write(codec, WM8903_POWER_MANAGEMENT_6, CtrlReg); #if 0 SidetoneCtrlReg = (0x1<<2) | (0x2<<0); SideToneAtenuation = 12 ; SidetoneCtrlReg |= (SideToneAtenuation<<8) | (SideToneAtenuation<<4); snd_soc_write(codec, R20_SIDETONE_CTRL, SidetoneCtrlReg); #endif CtrlReg = snd_soc_read(codec, R29_DRC_1); CtrlReg |= 0x3; /*mic volume 18 db */ snd_soc_write(codec, R29_DRC_1, CtrlReg); } return 0; }
static int mapasoc_be_dei2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int freq_in, freq_out, sspa_mclk, sysclk, sspa_div; /* * Now, hard code here, suppose change it according to channel num * the channel allocation.. */ unsigned int if1_tx_channel[2] = {3, 1}; unsigned int if1_rx_channel[2] = {7, 5}; unsigned int if2_tx_channel[2] = {2, 0}; unsigned int if2_rx_channel[2] = {6, 4}; freq_in = 26000000; if (params_rate(params) > 11025) { freq_out = params_rate(params) * 512; sysclk = 11289600; sspa_mclk = params_rate(params) * 64; } else { freq_out = params_rate(params) * 1024; sysclk = 11289600; sspa_mclk = params_rate(params) * 64; } sspa_div = freq_out; do_div(sspa_div, sspa_mclk); #if 0 snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); #else snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); #endif snd_soc_dai_set_sysclk(cpu_dai, AUDIO_PLL, freq_out, 0); /* set the interface to 44.1k sample rate */ snd_soc_dai_set_clkdiv(cpu_dai, 0, 0x13721fbd); /* * set slot for both cpu_dai and codec dai, * enable L1/R1 channel */ if (cpu_dai->id == 2) { snd_soc_dai_set_channel_map(cpu_dai, 2, if1_tx_channel, 2, if1_rx_channel); snd_soc_dai_set_channel_map(codec_dai, 2, if1_rx_channel, 2, if1_tx_channel); } else if (cpu_dai->id == 3) { snd_soc_dai_set_channel_map(cpu_dai, 2, if2_tx_channel, 2, if2_rx_channel); snd_soc_dai_set_channel_map(codec_dai, 2, if2_rx_channel, 2, if2_tx_channel); } /* set codec sysclk */ snd_soc_dai_set_sysclk(codec_dai, 0, 0, 1); return 0; }
static int smdk_wm8580_pcm_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int rfs, ret; switch (params_rate(params)) { case 8000: break; default: printk(KERN_ERR "%s:%d Sampling Rate %u not supported!\n", __func__, __LINE__, params_rate(params)); return -EINVAL; } rfs = mclk_freq / params_rate(params) / 2; /* */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; /* */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; if (mclk_freq == xtal_freq) { ret = snd_soc_dai_set_sysclk(codec_dai, WM8580_CLKSRC_MCLK, mclk_freq, SND_SOC_CLOCK_IN); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK, WM8580_CLKSRC_MCLK); if (ret < 0) return ret; } else { ret = snd_soc_dai_set_sysclk(codec_dai, WM8580_CLKSRC_PLLA, mclk_freq, SND_SOC_CLOCK_IN); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(codec_dai, WM8580_MCLK, WM8580_CLKSRC_PLLA); if (ret < 0) return ret; ret = snd_soc_dai_set_pll(codec_dai, WM8580_PLLA, 0, xtal_freq, mclk_freq); if (ret < 0) return ret; } /* */ ret = snd_soc_dai_set_sysclk(cpu_dai, S3C_PCM_CLKSRC_MUX, mclk_freq, SND_SOC_CLOCK_IN); if (ret < 0) return ret; /* */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C_PCM_SCLK_PER_FS, rfs); if (ret < 0) return ret; return 0; }
static int seaboard_asoc_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_codec *codec = rtd->codec; struct snd_soc_card *card = codec->card; struct tegra_seaboard *seaboard = snd_soc_card_get_drvdata(card); int srate, mclk, mclk_change; int err; srate = params_rate(params); switch (srate) { case 64000: case 88200: case 96000: mclk = 128 * srate; break; default: mclk = 256 * srate; break; } /* FIXME: Codec only requires >= 3MHz if OSR==0 */ while (mclk < 6000000) mclk *= 2; err = tegra_asoc_utils_set_rate(&seaboard->util_data, srate, mclk, &mclk_change); if (err < 0) { dev_err(card->dev, "Can't configure clocks\n"); return err; } err = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (err < 0) { dev_err(card->dev, "codec_dai fmt not set\n"); return err; } err = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (err < 0) { dev_err(card->dev, "cpu_dai fmt not set\n"); return err; } if (mclk_change) { err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk, SND_SOC_CLOCK_IN); if (err < 0) { dev_err(card->dev, "codec_dai clock not set\n"); return err; } } return 0; }
static int raumfeld_cs4270_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned int fmt, clk = 0; int ret = 0; switch (params_rate(params)) { case 44100: set_max9485_clk(MAX9485_MCLK_FREQ_112896); clk = 11289600; break; case 48000: set_max9485_clk(MAX9485_MCLK_FREQ_122880); clk = 12288000; break; case 88200: set_max9485_clk(MAX9485_MCLK_FREQ_225792); clk = 22579200; break; case 96000: set_max9485_clk(MAX9485_MCLK_FREQ_245760); clk = 24576000; break; default: return -EINVAL; } fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS; /* setup the CODEC DAI */ ret = snd_soc_dai_set_fmt(codec_dai, fmt); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(codec_dai, 0, clk, 0); if (ret < 0) return ret; /* setup the CPU DAI */ ret = snd_soc_dai_set_pll(cpu_dai, 0, 0, 0, clk); if (ret < 0) return ret; ret = snd_soc_dai_set_fmt(cpu_dai, fmt); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, PXA_SSP_DIV_SCR, 4); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(cpu_dai, PXA_SSP_CLK_EXT, clk, 1); if (ret < 0) return ret; return 0; }
int mop500_ab8500_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct device *dev = rtd->card->dev; unsigned int fmt; int channels, ret = 0, driver_mode, slots; unsigned int sw_codec, sw_cpu; bool is_playback; dev_dbg(dev, "%s: Enter\n", __func__); dev_dbg(dev, "%s: substream->pcm->name = %s\n" "substream->pcm->id = %s.\n" "substream->name = %s.\n" "substream->number = %d.\n", __func__, substream->pcm->name, substream->pcm->id, substream->name, substream->number); channels = params_channels(params); switch (params_format(params)) { case SNDRV_PCM_FORMAT_S32_LE: sw_cpu = 32; break; case SNDRV_PCM_FORMAT_S16_LE: sw_cpu = 16; break; default: return -EINVAL; } /* Setup codec depending on driver-mode */ if (channels == 8) driver_mode = DRIVERMODE_CODEC_ONLY; else driver_mode = DRIVERMODE_NORMAL; dev_dbg(dev, "%s: Driver-mode: %s.\n", __func__, (driver_mode == DRIVERMODE_NORMAL) ? "NORMAL" : "CODEC_ONLY"); /* Setup format */ if (driver_mode == DRIVERMODE_NORMAL) { fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CONT; } else { fmt = SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_GATED; } ret = snd_soc_dai_set_fmt(codec_dai, fmt); if (ret < 0) { dev_err(dev, "%s: ERROR: snd_soc_dai_set_fmt failed for codec_dai (ret = %d)!\n", __func__, ret); return ret; } ret = snd_soc_dai_set_fmt(cpu_dai, fmt); if (ret < 0) { dev_err(dev, "%s: ERROR: snd_soc_dai_set_fmt failed for cpu_dai (ret = %d)!\n", __func__, ret); return ret; } /* Setup TDM-slots */ is_playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); switch (channels) { case 1: slots = 16; tx_slots = (is_playback) ? TX_SLOT_MONO : 0; rx_slots = (is_playback) ? 0 : RX_SLOT_MONO; break; case 2: slots = 16; tx_slots = (is_playback) ? TX_SLOT_STEREO : 0; rx_slots = (is_playback) ? 0 : RX_SLOT_STEREO; break; case 8: slots = 16; tx_slots = (is_playback) ? TX_SLOT_8CH : 0; rx_slots = (is_playback) ? 0 : RX_SLOT_8CH; break; default: return -EINVAL; } if (driver_mode == DRIVERMODE_NORMAL) sw_codec = sw_cpu; else sw_codec = 20; dev_dbg(dev, "%s: CPU-DAI TDM: TX=0x%04X RX=0x%04x\n", __func__, tx_slots, rx_slots); ret = snd_soc_dai_set_tdm_slot(cpu_dai, tx_slots, rx_slots, slots, sw_cpu); if (ret) return ret; dev_dbg(dev, "%s: CODEC-DAI TDM: TX=0x%04X RX=0x%04x\n", __func__, tx_slots, rx_slots); ret = snd_soc_dai_set_tdm_slot(codec_dai, tx_slots, rx_slots, slots, sw_codec); if (ret) return ret; return 0; }
static int s3c24xx_uda134x_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned int clk = 0; int ret = 0; int clk_source, fs_mode; unsigned long rate = params_rate(params); long err, cerr; unsigned int div; int i, bi; err = 999999; bi = 0; for (i = 0; i < 2*33; i++) { cerr = rates[i] - rate; if (cerr < 0) cerr = -cerr; if (cerr < err) { err = cerr; bi = i; } } if (bi / 33 == 1) fs_mode = S3C2410_IISMOD_256FS; else fs_mode = S3C2410_IISMOD_384FS; if (bi % 33 == 0) { clk_source = S3C24XX_CLKSRC_MPLL; div = 1; } else { clk_source = S3C24XX_CLKSRC_PCLK; div = bi % 33; } pr_debug("%s desired rate %lu, %d\n", __func__, rate, bi); clk = (fs_mode == S3C2410_IISMOD_384FS ? 384 : 256) * rate; pr_debug("%s will use: %s %s %d sysclk %d err %ld\n", __func__, fs_mode == S3C2410_IISMOD_384FS ? "384FS" : "256FS", clk_source == S3C24XX_CLKSRC_MPLL ? "MPLLin" : "PCLK", div, clk, err); if ((err * 100 / rate) > 5) { printk(KERN_ERR "S3C24XX_UDA134X: effective frequency " "too different from desired (%ld%%)\n", err * 100 / rate); return -EINVAL; } ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(cpu_dai, clk_source , clk, SND_SOC_CLOCK_IN); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK, fs_mode); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_BCLK, S3C2410_IISMOD_32FS); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, S3C24XX_PRESCALE(div, div)); if (ret < 0) return ret; /* set the codec system clock for DAC and ADC */ ret = snd_soc_dai_set_sysclk(codec_dai, 0, clk, SND_SOC_CLOCK_OUT); if (ret < 0) return ret; return 0; }
/* * omap4_hw_params * This function is to configure the Machine Driver */ static int omap4_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; // struct snd_soc_codec *codec = rtd->codec; void __iomem *phymux_base = NULL; int ret, gpio_status; u32 phy_val; DBG("%s: Entered\n", __func__); /* Recording will not happen if headset is not inserted */ gpio_status = gpio_get_value(HEADSET_DETECT_GPIO_PIN); // if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) { // fm34_mode_switch(gpio_status); // printk(KERN_INFO "FM34 mode and interface switch..\n"); // } /* Set codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) { printk(KERN_ERR "can't set codec DAI configuration\n"); return ret; } DBG("snd_soc_dai_set_fmt passed..\n"); /* Set cpu DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) { printk(KERN_ERR "can't set cpu DAI configuration\n"); return ret; } DBG("snd_soc_dai_set_fmt passed...\n"); /* Enabling the 19.2 Mhz Master Clock Output from OMAP4 for KC1 Board */ // phymux_base = ioremap(0x4a30a000, 0x1000); // __raw_writel(0x00010100, phymux_base + 0x318); /* Enabling the 19.2 Mhz Master Clock Output from OMAP4 for Acclaim Board */ phymux_base = ioremap(0x4A30A000, 0x1000); phy_val = __raw_readl(phymux_base + 0x0314); phy_val = (phy_val & 0xFFF0FEFF) | (0x00010100); __raw_writel(phy_val, phymux_base + 0x0314); iounmap(phymux_base); /* Added the test code to configure the McBSP4 CONTROL_MCBSP_LP * register. This register ensures that the FSX and FSR on McBSP4 are * internally short and both of them see the same signal from the * External Audio Codec. */ // phymux_base = ioremap(0x4a100000, 0x1000); // __raw_writel(0xC0000000, phymux_base + 0x61c); /* Set the codec system clock for DAC and ADC. The * third argument is specific to the board being used. */ ret = snd_soc_dai_set_sysclk(codec_dai, 0, AIC31XX_FREQ_19200000, SND_SOC_CLOCK_IN); if (ret < 0) { printk(KERN_ERR "can't set codec system clock\n"); return ret; } DBG("omap4_hw_params passed...\n"); return 0; }
static int fsi_da7210_init(struct snd_soc_codec *codec) { return snd_soc_dai_set_fmt(&da7210_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); }
static int tegra_bt_sco_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_codec *codec = rtd->codec; struct snd_soc_card *card = codec->card; struct tegra_wm8753 *machine = snd_soc_card_get_drvdata(card); struct tegra_asoc_platform_data *pdata = machine->pdata; int srate, mclk, min_mclk, i2s_daifmt; int err; srate = params_rate(params); switch (srate) { case 11025: case 22050: case 44100: case 88200: mclk = 11289600; break; case 8000: case 16000: case 32000: case 48000: case 64000: case 96000: mclk = 12288000; break; default: return -EINVAL; } min_mclk = 64 * srate; err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk); if (err < 0) { if (!(machine->util_data.set_mclk % min_mclk)) mclk = machine->util_data.set_mclk; else { dev_err(card->dev, "Can't configure clocks\n"); return err; } } tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1); i2s_daifmt = SND_SOC_DAIFMT_NB_NF; i2s_daifmt |= pdata->i2s_param[BT_SCO].is_i2s_master ? SND_SOC_DAIFMT_CBS_CFS : SND_SOC_DAIFMT_CBM_CFM; switch (pdata->i2s_param[BT_SCO].i2s_mode) { case TEGRA_DAIFMT_I2S : i2s_daifmt |= SND_SOC_DAIFMT_I2S; break; case TEGRA_DAIFMT_DSP_A : i2s_daifmt |= SND_SOC_DAIFMT_DSP_A; break; case TEGRA_DAIFMT_DSP_B : i2s_daifmt |= SND_SOC_DAIFMT_DSP_B; break; case TEGRA_DAIFMT_LEFT_J : i2s_daifmt |= SND_SOC_DAIFMT_LEFT_J; break; case TEGRA_DAIFMT_RIGHT_J : i2s_daifmt |= SND_SOC_DAIFMT_RIGHT_J; break; default : dev_err(card->dev, "Can't configure i2s format\n"); return -EINVAL; } err = snd_soc_dai_set_fmt(cpu_dai, i2s_daifmt); if (err < 0) { dev_err(card->dev, "cpu_dai fmt not set\n"); return err; } #ifdef CONFIG_ARCH_TEGRA_2x_SOC err = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAP_SEL_DAC2, TEGRA20_DAS_DAP_ID_4); if (err < 0) { dev_err(card->dev, "failed to set dac-dap path\n"); return err; } err = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_4, TEGRA20_DAS_DAP_SEL_DAC2); if (err < 0) { dev_err(card->dev, "failed to set dac-dap path\n"); return err; } #endif return 0; }
static int daudio0_set_clk(void) { int ret = 0; u32 freq_in = 24000000; u32 freq_out = 22579200; struct snd_soc_pcm_runtime *rtd = runtime; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned long sample_rate = 44100; switch (sample_rate) { case 8000: case 16000: case 32000: case 64000: case 128000: case 12000: case 24000: case 48000: case 96000: case 192000: freq_out = 24576000; break; } pr_info("%s,line:%d,freq_in:%d,daudio_pcm_select:%d,audio_format:%d,signal_inversion:%d\n",__func__,__LINE__, freq_in,daudio_pcm_select,audio_format,signal_inversion); /* set the codec FLL */ ret = snd_soc_dai_set_pll(codec_dai, AC100_MCLK1, 0, freq_in, freq_out); if (ret < 0) { return ret; } /*set cpu_dai clk*/ ret = snd_soc_dai_set_sysclk(cpu_dai, 0 , freq_out, daudio_pcm_select); if (ret < 0) { return ret; } /*set codec_dai clk*/ ret = snd_soc_dai_set_sysclk(codec_dai, AIF1_CLK , freq_out, daudio_pcm_select); if (ret < 0) { return ret; } /* * ac100: master. AP: slave */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); if (ret < 0) { return ret; } ret = snd_soc_dai_set_fmt(cpu_dai, (audio_format | (signal_inversion<<8) | SND_SOC_DAIFMT_CBM_CFM)); if (ret < 0) { return ret; } ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, sample_rate); if (ret < 0) { return ret; } return 0; }
static int tegra_wm8753_voice_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_codec *codec = rtd->codec; struct snd_soc_card *card = codec->card; struct tegra_wm8753 *machine = snd_soc_card_get_drvdata(card); int srate, mclk, i2s_daifmt, sys_clk; int err, pcmdiv, vxclkdiv; srate = params_rate(params); switch (srate) { case 8000: case 16000: case 24000: case 32000: case 48000: case 64000: case 96000: mclk = 12288000; break; case 11025: case 22050: case 44100: case 88200: mclk = 11289600; break; default: mclk = 12000000; break; } err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk); if (err < 0) { if (!(machine->util_data.set_mclk % mclk)) mclk = machine->util_data.set_mclk; else { dev_err(card->dev, "Can't configure clocks\n"); return err; } } tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1); i2s_daifmt = SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM; i2s_daifmt |= SND_SOC_DAIFMT_DSP_A; err = snd_soc_dai_set_fmt(codec_dai, i2s_daifmt); if (err < 0) { dev_err(card->dev, "codec_dai fmt not set\n"); return err; } sys_clk = machine->util_data.set_mclk; err = snd_soc_dai_set_sysclk(codec_dai, WM8753_PCMCLK, sys_clk, SND_SOC_CLOCK_IN); if (err < 0) { dev_err(card->dev, "codec_dai clock not set\n"); return err; } err = snd_soc_dai_set_pll(codec_dai, WM8753_PLL2, 0, sys_clk, 12288000); if (err < 0) { dev_err(card->dev, "codec_dai pll not set\n"); return err; } if (params_rate(params) == 8000) { pcmdiv = WM8753_PCM_DIV_6; /* BB expecting 2048Khz bclk */ vxclkdiv = WM8753_VXCLK_DIV_1; } else if (params_rate(params) == 16000) { pcmdiv = WM8753_PCM_DIV_3; /* BB expecting 2048Khz bclk */ vxclkdiv = WM8753_VXCLK_DIV_2; } else { dev_err(card->dev, "codec_dai unsupported voice rate\n"); return -EINVAL; } snd_soc_dai_set_clkdiv(codec_dai, WM8753_VXCLKDIV, vxclkdiv); snd_soc_dai_set_clkdiv(codec_dai, WM8753_PCMDIV, pcmdiv); machine->is_call_mode_bt = 0; return 0; }
/* Switch the FLL */ ret = snd_soc_dai_set_pll(codec_dai, WM8994_FLL1, WM8994_FLL_SRC_MCLK1, MIDAS_DEFAULT_MCLK1, pll_out); if (ret < 0) dev_err(codec_dai->dev, "Unable to start FLL1: %d\n", ret); ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_FLL1, pll_out, SND_SOC_CLOCK_IN); if (ret < 0) { dev_err(codec_dai->dev, "Unable to switch to FLL1: %d\n", ret); return ret; } ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_OPCLK, 0, MOD_OPCLK_PCLK); if (ret < 0) return ret; #else midas_start_fll1(codec_dai); #endif if (ret < 0) return ret; dev_info(codec_dai->dev, "%s --\n", __func__); return 0; } #else /* CONFIG_SND_SAMSUNG_I2S_MASTER */ static int midas_wm1811_aif1_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int bfs, psr, rfs, ret; unsigned long rclk; switch (params_format(params)) { case SNDRV_PCM_FORMAT_U24: case SNDRV_PCM_FORMAT_S24: bfs = 48; break; case SNDRV_PCM_FORMAT_U16_LE: case SNDRV_PCM_FORMAT_S16_LE: bfs = 32; break; default: return -EINVAL; } switch (params_rate(params)) { case 16000: case 22050: case 24000: case 32000: case 44100: case 48000: case 88200: case 96000: if (bfs == 48) rfs = 384; else rfs = 256; break; case 64000: rfs = 384; break; case 8000: case 11025: case 12000: if (bfs == 48) rfs = 768; else rfs = 512; break; default: return -EINVAL; } rclk = params_rate(params) * rfs; switch (rclk) { case 4096000: case 5644800: case 6144000: case 8467200: case 9216000: psr = 8; break; case 8192000: case 11289600: case 12288000: case 16934400: case 18432000: psr = 4; break; case 22579200: case 24576000: case 33868800: case 36864000: psr = 2; break; case 67737600: case 73728000: psr = 1; break; default: printk(KERN_INFO "Not yet supported!\n"); return -EINVAL; } set_epll_rate(rclk * psr); ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(codec_dai, WM8994_SYSCLK_MCLK1, rclk, SND_SOC_CLOCK_IN); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_CDCLK, 0, SND_SOC_CLOCK_OUT); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, SAMSUNG_I2S_DIV_BCLK, bfs); if (ret < 0) return ret; return 0; }
static int tegra_wm8753_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_codec *codec = codec_dai->codec; struct snd_soc_card *card = codec->card; struct tegra_wm8753 *machine = snd_soc_card_get_drvdata(card); struct tegra_asoc_platform_data *pdata = machine->pdata; int srate, mclk, i2s_daifmt; int err, rate; srate = params_rate(params); switch (srate) { case 8000: case 16000: case 24000: case 32000: case 48000: case 64000: case 96000: mclk = 12288000; break; case 11025: case 22050: case 44100: case 88200: mclk = 11289600; break; default: mclk = 12000000; break; } err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk); if (err < 0) { if (!(machine->util_data.set_mclk % mclk)) mclk = machine->util_data.set_mclk; else { dev_err(card->dev, "Can't configure clocks\n"); return err; } } tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1); rate = clk_get_rate(machine->util_data.clk_cdev1); i2s_daifmt = SND_SOC_DAIFMT_NB_NF; i2s_daifmt |= pdata->i2s_param[HIFI_CODEC].is_i2s_master ? SND_SOC_DAIFMT_CBS_CFS : SND_SOC_DAIFMT_CBM_CFM; /* Use DSP mode for mono on Tegra20 */ if ((params_channels(params) != 2) && machine_is_whistler()) { i2s_daifmt |= SND_SOC_DAIFMT_DSP_A; } else { switch (pdata->i2s_param[HIFI_CODEC].i2s_mode) { case TEGRA_DAIFMT_I2S : i2s_daifmt |= SND_SOC_DAIFMT_I2S; break; case TEGRA_DAIFMT_DSP_A : i2s_daifmt |= SND_SOC_DAIFMT_DSP_A; break; case TEGRA_DAIFMT_DSP_B : i2s_daifmt |= SND_SOC_DAIFMT_DSP_B; break; case TEGRA_DAIFMT_LEFT_J : i2s_daifmt |= SND_SOC_DAIFMT_LEFT_J; break; case TEGRA_DAIFMT_RIGHT_J : i2s_daifmt |= SND_SOC_DAIFMT_RIGHT_J; break; default : dev_err(card->dev, "Can't configure i2s format\n"); return -EINVAL; } } err = snd_soc_dai_set_fmt(codec_dai, i2s_daifmt); if (err < 0) { dev_err(card->dev, "codec_dai fmt not set\n"); return err; } err = snd_soc_dai_set_fmt(cpu_dai, i2s_daifmt); if (err < 0) { dev_err(card->dev, "cpu_dai fmt not set\n"); return err; } err = snd_soc_dai_set_sysclk(codec_dai, 0, rate, SND_SOC_CLOCK_IN); if (err < 0) { dev_err(card->dev, "codec_dai clock not set\n"); return err; } #ifdef CONFIG_ARCH_TEGRA_2x_SOC err = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAP_SEL_DAC1, TEGRA20_DAS_DAP_ID_1); if (err < 0) { dev_err(card->dev, "failed to set dap-dac path\n"); return err; } err = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_1, TEGRA20_DAS_DAP_SEL_DAC1); if (err < 0) { dev_err(card->dev, "failed to set dac-dap path\n"); return err; } #endif return 0; }
static int tegra_max98095_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_codec *codec = rtd->codec; struct snd_soc_card *card = codec->card; struct tegra_max98095 *machine = snd_soc_card_get_drvdata(card); #ifndef CONFIG_ARCH_TEGRA_2x_SOC struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai); #endif unsigned int srate, mclk, sample_size; int err; switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: sample_size = 16; break; default: return -EINVAL; } srate = params_rate(params); switch (srate) { case 8000: case 16000: case 24000: case 32000: case 48000: case 64000: case 96000: mclk = 12288000; break; case 11025: case 22050: case 44100: case 88200: mclk = 11289600; break; default: mclk = 12000000; break; } err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk); if (err < 0) { if (!(machine->util_data.set_mclk % mclk)) mclk = machine->util_data.set_mclk; else { dev_err(card->dev, "Can't configure clocks\n"); return err; } } tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1); err = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (err < 0) { dev_err(card->dev, "codec_dai fmt not set\n"); return err; } err = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (err < 0) { dev_err(card->dev, "cpu_dai fmt not set\n"); return err; } err = snd_soc_dai_set_sysclk(codec_dai, 0, mclk, SND_SOC_CLOCK_IN); if (err < 0) { dev_err(card->dev, "codec_dai clock not set\n"); return err; } #ifndef CONFIG_ARCH_TEGRA_2x_SOC if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) tegra_max98095_set_dam_cif(i2s->dam_ifc, srate, params_channels(params), sample_size); #endif return 0; }
static int rk29_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned int pll_out = 0, dai_fmt = rtd->dai_link->dai_fmt; int ret; int div_bclk,div_mclk; DBG("Enter::%s----%d\n", __FUNCTION__, __LINE__); /* set codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, dai_fmt); if (ret < 0) { printk("%s():failed to set the format for codec side\n", __FUNCTION__); return ret; } /* set cpu DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, dai_fmt); if (ret < 0) { printk("%s():failed to set the format for cpu side\n", __FUNCTION__); return ret; } switch(params_rate(params)) { case 8000: case 16000: case 24000: case 32000: case 48000: case 96000: pll_out = 12288000; break; case 11025: case 22050: case 44100: case 88200: pll_out = 11289600; break; case 176400: pll_out = 11289600*2; break; case 192000: pll_out = 12288000*2; break; default: DBG("Enter:%s, %d, Error rate=%d\n",__FUNCTION__,__LINE__,params_rate(params)); return -EINVAL; break; } DBG("Enter:%s, %d, rate=%d\n",__FUNCTION__,__LINE__,params_rate(params)); snd_soc_dai_set_sysclk(codec_dai, 0, pll_out, SND_SOC_CLOCK_IN); div_bclk = 127; div_mclk = pll_out/(params_rate(params)*128) - 1; snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK,div_bclk); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, div_mclk); return 0; }
static int pacific_hdmi_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; int pll, div, sclk, bfs, psr, rfs, ret; unsigned long rclk; switch (params_format(params)) { case SNDRV_PCM_FORMAT_U24: case SNDRV_PCM_FORMAT_S24: bfs = 64; break; case SNDRV_PCM_FORMAT_U16_LE: case SNDRV_PCM_FORMAT_S16_LE: bfs = 32; break; default: return -EINVAL; } switch (params_rate(params)) { case 48000: case 96000: case 192000: if (bfs == 64) rfs = 512; else if (bfs == 48) rfs = 384; else rfs = 256; break; default: return -EINVAL; } rclk = params_rate(params) * rfs; switch (rclk) { case 12288000: case 18432000: psr = 4; break; case 24576000: case 36864000: psr = 2; break; case 49152000: case 73728000: case 98304000: psr = 1; break; default: pr_err("Not yet supported!\n"); return -EINVAL; } /* Set AUD_PLL frequency */ sclk = rclk * psr; for (div = 2; div <= 16; div++) { if (sclk * div > PACIFIC_AUD_PLL_FREQ) break; } pll = sclk * (div - 1); set_aud_pll_rate(pll); /* Set CPU DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_CDCLK, 0, SND_SOC_CLOCK_OUT); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_OPCLK, 0, MOD_OPCLK_PCLK); if (ret < 0) return ret; ret = snd_soc_dai_set_sysclk(cpu_dai, SAMSUNG_I2S_RCLKSRC_1, 0, 0); if (ret < 0) return ret; ret = snd_soc_dai_set_clkdiv(cpu_dai, SAMSUNG_I2S_DIV_BCLK, bfs); if (ret < 0) return ret; return 0; }
static int rx1950_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_dai *codec_dai = rtd->codec_dai; int div; int ret; unsigned int rate = params_rate(params); int clk_source, fs_mode; switch (rate) { case 16000: case 48000: clk_source = S3C24XX_CLKSRC_PCLK; fs_mode = S3C2410_IISMOD_256FS; div = s3c24xx_i2s_get_clockrate() / (256 * rate); if (s3c24xx_i2s_get_clockrate() % (256 * rate) > (128 * rate)) div++; break; case 44100: case 88200: clk_source = S3C24XX_CLKSRC_MPLL; fs_mode = S3C2410_IISMOD_384FS; div = 1; break; default: printk(KERN_ERR "%s: rate %d is not supported\n", __func__, rate); return -EINVAL; } /* set codec DAI configuration */ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; /* set cpu DAI configuration */ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (ret < 0) return ret; /* select clock source */ ret = snd_soc_dai_set_sysclk(cpu_dai, clk_source, rate, SND_SOC_CLOCK_OUT); if (ret < 0) return ret; /* set MCLK division for sample rate */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_MCLK, fs_mode); if (ret < 0) return ret; /* set BCLK division for sample rate */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_BCLK, S3C2410_IISMOD_32FS); if (ret < 0) return ret; /* set prescaler division for sample rate */ ret = snd_soc_dai_set_clkdiv(cpu_dai, S3C24XX_DIV_PRESCALER, S3C24XX_PRESCALE(div, div)); if (ret < 0) return ret; return 0; }
static int rk29_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; unsigned int pll_out = 0; int ret; DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); /*by Vincent Hsiung for EQ Vol Change*/ #define HW_PARAMS_FLAG_EQVOL_ON 0x21 #define HW_PARAMS_FLAG_EQVOL_OFF 0x22 if (codec_dai->driver->ops->hw_params && ((params->flags == HW_PARAMS_FLAG_EQVOL_ON) || (params->flags == HW_PARAMS_FLAG_EQVOL_OFF))) { ret = codec_dai->driver->ops->hw_params(substream, params, codec_dai); //by Vincent DBG("Enter::%s----%d\n",__FUNCTION__,__LINE__); } else { /* set codec DAI configuration */ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE) ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); #endif #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER) ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM ); #endif if (ret < 0) return ret; /* set cpu DAI configuration */ #if defined (CONFIG_SND_RK29_CODEC_SOC_SLAVE) ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); #endif #if defined (CONFIG_SND_RK29_CODEC_SOC_MASTER) ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); #endif if (ret < 0) return ret; } switch(params_rate(params)) { case 8000: case 16000: case 24000: case 32000: case 48000: pll_out = 12288000; break; case 11025: case 22050: case 44100: pll_out = 11289600; break; default: DBG("Enter:%s, %d, Error rate=%d\n", __FUNCTION__, __LINE__, params_rate(params)); return -EINVAL; break; } DBG("Enter:%s, %d, rate=%d\n", __FUNCTION__, __LINE__, params_rate(params)); /*Set the system clk for codec*/ ret = snd_soc_dai_set_sysclk(codec_dai, 0, pll_out, SND_SOC_CLOCK_IN); if (ret < 0) { DBG("rk29_hw_params_rt3261:failed to set the sysclk for codec side\n"); return ret; } snd_soc_dai_set_sysclk(cpu_dai, 0, pll_out, 0); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_BCLK, (pll_out/4)/params_rate(params)-1); snd_soc_dai_set_clkdiv(cpu_dai, ROCKCHIP_DIV_MCLK, 3); DBG("Enter:%s, %d, pll_out/4/params_rate(params) = %d \n", __FUNCTION__, __LINE__, (pll_out/4)/params_rate(params)); return 0; }
static int tegra_bt_sco_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_card *card = rtd->card; struct tegra_wm8903 *machine = snd_soc_card_get_drvdata(card); int srate, mclk, min_mclk; int err; srate = params_rate(params); switch (srate) { case 11025: case 22050: case 44100: case 88200: mclk = 11289600; break; case 8000: case 16000: case 32000: case 48000: case 64000: case 96000: mclk = 12288000; break; default: return -EINVAL; } min_mclk = 64 * srate; err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk); if (err < 0) { if (!(machine->util_data.set_mclk % min_mclk)) mclk = machine->util_data.set_mclk; else { dev_err(card->dev, "Can't configure clocks\n"); return err; } } tegra_asoc_utils_lock_clk_rate(&machine->util_data, 1); err = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS); if (err < 0) { dev_err(card->dev, "cpu_dai fmt not set\n"); return err; } #ifdef CONFIG_ARCH_TEGRA_2x_SOC err = tegra20_das_connect_dac_to_dap(TEGRA20_DAS_DAP_SEL_DAC2, TEGRA20_DAS_DAP_ID_4); if (err < 0) { dev_err(card->dev, "failed to set dac-dap path\n"); return err; } err = tegra20_das_connect_dap_to_dac(TEGRA20_DAS_DAP_ID_4, TEGRA20_DAS_DAP_SEL_DAC2); if (err < 0) { dev_err(card->dev, "failed to set dac-dap path\n"); return err; } #endif return 0; }