void s3c_i2c1_cfg_gpio(struct platform_device *dev)
{
if (soc_is_exynos5250())
s3c_gpio_cfgall_range(EXYNOS5_GPB3(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5260())
s3c_gpio_cfgall_range(EXYNOS5260_GPB4(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5410())
s3c_gpio_cfgall_range(EXYNOS5410_GPB3(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5420())
s3c_gpio_cfgall_range(EXYNOS5420_GPB3(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos3250())
s3c_gpio_cfgall_range(EXYNOS3_GPD1(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else /* EXYNOS4210, EXYNOS4212, and EXYNOS4412 */
s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
}
int s3c_irq_wake(struct irq_data *data, unsigned int state)
{
unsigned long irqbit;
unsigned int irq_rtc_tic, irq_rtc_alarm;
#ifdef CONFIG_ARCH_EXYNOS
if (soc_is_exynos3250()) {
irq_rtc_tic = EXYNOS3250_IRQ_RTC_TIC;
irq_rtc_alarm = EXYNOS3250_IRQ_RTC_ALARM;
} else if (soc_is_exynos5250()) {
irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC;
irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM;
} else {
irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC;
irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM;
}
#else
irq_rtc_tic = IRQ_RTC_TIC;
irq_rtc_alarm = IRQ_RTC_ALARM;
#endif
if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
if (!state)
s3c_irqwake_intmask |= irqbit;
else
s3c_irqwake_intmask &= ~irqbit;
} else {
return -ENOENT;
}
return 0;
}
void s3c_adc_phy_init(void)
{
u32 reg;
if (soc_is_exynos5250() || soc_is_exynos4415() ||
soc_is_exynos3470() || soc_is_exynos3250()) {
reg = __raw_readl(EXYNOS5250_ADC_PHY_CONTROL);
reg |= EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5250_ADC_PHY_CONTROL);
} else if (soc_is_exynos5410() || soc_is_exynos5420()) {
reg = __raw_readl(EXYNOS5410_ADC_PHY_CONTROL);
reg |= EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5410_ADC_PHY_CONTROL);
} else if (soc_is_exynos5260()) {
/* ADC phy select */
reg = readl(EXYNOS5260_SYSCON_PERI_PHY_SELECT);
if (reg & EXYNOS5260_SYSCON_PERI_PHY_SELECT_ISP_ONLY)
reg &= ~(EXYNOS5260_SYSCON_PERI_PHY_SELECT_ISP_ONLY);
writel(reg, EXYNOS5260_SYSCON_PERI_PHY_SELECT);
reg = __raw_readl(EXYNOS5260_ADC_PHY_CONTROL);
reg |= EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5260_ADC_PHY_CONTROL);
}
}
void exynos_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int i;
if (soc_is_exynos3250()) {
exynos3250_init_pmu();
if (mode == SYS_SLEEP) {
__raw_writel(0x00000BB8, EXYNOS3_XUSBXTI_DURATION);
__raw_writel(0x00000BB8, EXYNOS3_XXTI_DURATION);
__raw_writel(0x00001D4C,
EXYNOS3_EXT_REGULATOR_DURATION);
__raw_writel(0x00001D4C,
EXYNOS3_EXT_REGULATOR_COREBLK_DURATION);
}
}
if (soc_is_exynos5250())
exynos5_init_pmu();
for (i = 0; (exynos_pmu_config[i].reg != PMU_TABLE_END) ; i++)
__raw_writel(exynos_pmu_config[i].val[mode],
exynos_pmu_config[i].reg);
if (soc_is_exynos4412()) {
for (i = 0; exynos4412_pmu_config[i].reg != PMU_TABLE_END ; i++)
__raw_writel(exynos4412_pmu_config[i].val[mode],
exynos4412_pmu_config[i].reg);
}
}
static int __init exynos_pmu_init(void)
{
unsigned int value;
exynos_pmu_config = exynos4210_pmu_config;
if (soc_is_exynos3250()) {
/*
* To prevent form issuing new bus request form L2 memory system
* If core status is power down, should be set '1' to L2 power down
*/
value = __raw_readl(EXYNOS3_ARM_COMMON_OPTION);
value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
__raw_writel(value, EXYNOS3_ARM_COMMON_OPTION);
/* Enable USE_STANDBY_WFI for all CORE */
__raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
/*
* Set PSHOLD port for ouput high
*/
value = __raw_readl(S5P_PS_HOLD_CONTROL);
value |= S5P_PS_HOLD_OUTPUT_HIGH;
__raw_writel(value, S5P_PS_HOLD_CONTROL);
/*
* Enable signal for PSHOLD port
*/
value = __raw_readl(S5P_PS_HOLD_CONTROL);
value |= S5P_PS_HOLD_EN;
__raw_writel(value, S5P_PS_HOLD_CONTROL);
exynos_pmu_config = exynos3250_pmu_config;
pr_info("EXYNOS3250 PMU Initialize\n");
} else if (soc_is_exynos4210()) {
exynos_pmu_config = exynos4210_pmu_config;
pr_info("EXYNOS4210 PMU Initialize\n");
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos_pmu_config = exynos4x12_pmu_config;
pr_info("EXYNOS4x12 PMU Initialize\n");
} else if (soc_is_exynos5250()) {
/*
* When SYS_WDTRESET is set, watchdog timer reset request
* is ignored by power management unit.
*/
value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
value &= ~EXYNOS5_SYS_WDTRESET;
__raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
value &= ~EXYNOS5_SYS_WDTRESET;
__raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
exynos_pmu_config = exynos5250_pmu_config;
pr_info("EXYNOS5250 PMU Initialize\n");
} else {
pr_info("EXYNOS: PMU not supported\n");
}
return 0;
}
static void exynos_sfr_save(unsigned int i)
{
struct dw_mci *host = dw_mci_lpa_host[i];
dw_mci_save_sfr[i][0] = __raw_readl(host->regs + DWMCI_CTRL);
dw_mci_save_sfr[i][1] = __raw_readl(host->regs + DWMCI_PWREN);
dw_mci_save_sfr[i][2] = __raw_readl(host->regs + DWMCI_CLKDIV);
dw_mci_save_sfr[i][3] = __raw_readl(host->regs + DWMCI_CLKSRC);
dw_mci_save_sfr[i][4] = __raw_readl(host->regs + DWMCI_CLKENA);
dw_mci_save_sfr[i][5] = __raw_readl(host->regs + DWMCI_TMOUT);
dw_mci_save_sfr[i][6] = __raw_readl(host->regs + DWMCI_CTYPE);
dw_mci_save_sfr[i][7] = __raw_readl(host->regs + DWMCI_INTMASK);
dw_mci_save_sfr[i][8] = __raw_readl(host->regs + DWMCI_FIFOTH);
dw_mci_save_sfr[i][9] = __raw_readl(host->regs + DWMCI_UHS_REG);
dw_mci_save_sfr[i][10] = __raw_readl(host->regs + DWMCI_BMOD);
dw_mci_save_sfr[i][11] = __raw_readl(host->regs + DWMCI_PLDMND);
dw_mci_save_sfr[i][12] = __raw_readl(host->regs + DWMCI_DBADDR);
dw_mci_save_sfr[i][13] = __raw_readl(host->regs + DWMCI_IDINTEN);
dw_mci_save_sfr[i][14] = __raw_readl(host->regs + DWMCI_CLKSEL);
dw_mci_save_sfr[i][15] = __raw_readl(host->regs + DWMCI_CDTHRCTL);
if (soc_is_exynos3250() || soc_is_exynos4415() ||
soc_is_exynos5420() || soc_is_exynos5260() || soc_is_exynos3470()) {
dw_mci_save_sfr[i][16] = __raw_readl(host->regs +
DWMCI_DDR200_RDDQS_EN + 0x70);
dw_mci_save_sfr[i][17] = __raw_readl(host->regs +
DWMCI_DDR200_DLINE_CTRL + 0x70);
} else {
dw_mci_save_sfr[i][16] = __raw_readl(host->regs +
DWMCI_DDR200_RDDQS_EN);
dw_mci_save_sfr[i][17] = __raw_readl(host->regs +
DWMCI_DDR200_DLINE_CTRL);
}
}
void s3c_i2c4_cfg_gpio(struct platform_device *dev)
{
if (soc_is_exynos4210())
s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
else if (soc_is_exynos4212() || soc_is_exynos4412() || soc_is_exynos4415())
s3c_gpio_cfgall_range(EXYNOS4_GPB(0), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5250())
s3c_gpio_cfgall_range(EXYNOS5_GPA2(0), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
else if (soc_is_exynos5260())
s3c_gpio_cfgall_range(EXYNOS5260_GPB5(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
else if (soc_is_exynos3250())
s3c_gpio_cfgall_range(EXYNOS3_GPB(0), 2,
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
else
pr_err("failed to configure gpio for i2c4\n");
}
void __init exynos_dwmci_set_platdata(struct dw_mci_board *pd, u32 slot_id)
{
struct dw_mci_board *npd = NULL;
if ((soc_is_exynos4210()) || soc_is_exynos4212() ||
soc_is_exynos4412()) {
npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
&exynos4_device_dwmci);
} else if (soc_is_exynos5250() || soc_is_exynos5410() ||
soc_is_exynos5420() || soc_is_exynos5260()) {
if (slot_id < ARRAY_SIZE(exynos5_dwmci_devs))
npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
exynos5_dwmci_devs[slot_id]);
else
pr_err("%s: slot %d is not supported\n", __func__,
slot_id);
} else if ((soc_is_exynos3250()) || soc_is_exynos4415()) {
if (slot_id < ARRAY_SIZE(exynos4_dwmci_devs))
npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
exynos4_dwmci_devs[slot_id]);
else
pr_err("%s: slot %d is not supported\n", __func__,
slot_id);
} else if (soc_is_exynos3470()) {
if (slot_id < ARRAY_SIZE(exynos4_dwmci_devs))
npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
exynos4_dwmci_devs[slot_id]);
else
pr_err("%s: slot %d is not supported\n", __func__,
slot_id);
}
if (!npd)
return;
if (!npd->init)
npd->init = exynos_dwmci_init;
if (!npd->get_bus_wd)
npd->get_bus_wd = exynos_dwmci_get_bus_wd;
if (!npd->set_io_timing)
npd->set_io_timing = exynos_dwmci_set_io_timing;
if (!npd->get_ocr)
npd->get_ocr = exynos_dwmci_get_ocr;
if (!npd->clk_tbl)
npd->clk_tbl = exynos_dwmci_clk_rates;
if (!npd->cfg_smu)
npd->cfg_smu = exynos_dwmci_cfg_smu;
}
void __init smp_init_cpus(void)
{
void __iomem *scu_base = scu_base_addr();
unsigned int i, ncores;
if (soc_is_exynos4210() || soc_is_exynos4212() ||
soc_is_exynos5250() || soc_is_exynos3250())
ncores = 2;
else if (soc_is_exynos4412() || soc_is_exynos5410()
|| soc_is_exynos4415() || soc_is_exynos3470())
ncores = 4;
else if (soc_is_exynos5260())
#ifdef CONFIG_EXYNOS5_MP
ncores = NR_CPUS;
#else
ncores = read_cpuid_mpidr() & 0x100 ? 4 : 2;
#endif
else if (soc_is_exynos5420())
static void exynos_dwmci_cfg_smu(void *data, u32 action)
{
struct dw_mci *host = (struct dw_mci *)data;
if ((!soc_is_exynos5420() && !soc_is_exynos5260() &&
!soc_is_exynos4415() && !soc_is_exynos3250()) || action != 0)
return;
/* bypass mode */
if (host->pdata->ch_num != 2) {
__raw_writel(0, host->regs + DWMCI_MPSBEGIN0);
__raw_writel(0xFFFFFFFF, host->regs + DWMCI_MPSEND0);
__raw_writel(DWMCI_MPSCTRL_SECURE_READ_BIT |
DWMCI_MPSCTRL_SECURE_WRITE_BIT |
DWMCI_MPSCTRL_NON_SECURE_READ_BIT |
DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT |
DWMCI_MPSCTRL_VALID, host->regs + DWMCI_MPSCTRL0);
}
}
void s3c_adc_phy_exit(void)
{
u32 reg;
if (soc_is_exynos5250() || soc_is_exynos4415() ||
soc_is_exynos3470() || soc_is_exynos3250()) {
reg = __raw_readl(EXYNOS5250_ADC_PHY_CONTROL);
reg &= ~EXYNOS5_ADC_PHY_ENABLE;
reg |= EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5250_ADC_PHY_CONTROL);
} else if (soc_is_exynos5410() || soc_is_exynos5420()) {
reg = __raw_readl(EXYNOS5410_ADC_PHY_CONTROL);
reg &= ~EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5410_ADC_PHY_CONTROL);
} else if (soc_is_exynos5260()) {
reg = __raw_readl(EXYNOS5260_ADC_PHY_CONTROL);
reg &= ~EXYNOS5_ADC_PHY_ENABLE;
__raw_writel(reg, EXYNOS5260_ADC_PHY_CONTROL);
}
}
static int exynos_cpu_boot(int cpu)
{
/*
* Exynos3250 doesn't need to send smc command for secondary CPU boot
* because Exynos3250 removes WFE in secure mode.
*/
if (soc_is_exynos3250())
return 0;
/*
* The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
* But, Exynos4212 has only one secondary CPU so second parameter
* isn't used for informing secure firmware about CPU id.
*/
if (soc_is_exynos4212())
cpu = 0;
exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
return 0;
}
static int exynos_do_idle(unsigned long mode)
{
switch (mode) {
case FW_DO_IDLE_AFTR:
if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
exynos_save_cp15();
__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
sysram_ns_base_addr + 0x24);
__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
if (soc_is_exynos3250()) {
exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
SMC_POWERSTATE_IDLE, 0);
exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
SMC_POWERSTATE_IDLE, 0);
} else
exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
break;
case FW_DO_IDLE_SLEEP:
exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
}
return 0;
}
static int __init exynos_dma_init(void)
{
if (of_have_populated_dt())
return 0;
if (soc_is_exynos4210()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4210_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4210_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4212_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4212_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
} else if (soc_is_exynos4415()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4415_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos4415_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos4415_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos4415_pdma1_peri;
} else if (soc_is_exynos5250()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5250_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5250_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
} else if (soc_is_exynos5410()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5410_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos5410_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5410_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos5410_pdma1_peri;
} else if (soc_is_exynos5420()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5420_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos5420_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5420_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos5420_pdma1_peri;
exynos_adma0_pdata.nr_valid_peri =
ARRAY_SIZE(adma0_peri);
exynos_adma0_pdata.peri_id = adma0_peri;
} else if (soc_is_exynos5260()) {
exynos5260_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos5260_pdma0_peri);
exynos5260_pdma0_pdata.peri_id = exynos5260_pdma0_peri;
} else if (soc_is_exynos3470()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos3470_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos3470_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos3470_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos3470_pdma1_peri;
} else if (soc_is_exynos3250()) {
exynos_pdma0_pdata.nr_valid_peri =
ARRAY_SIZE(exynos3250_pdma0_peri);
exynos_pdma0_pdata.peri_id = exynos3250_pdma0_peri;
exynos_pdma1_pdata.nr_valid_peri =
ARRAY_SIZE(exynos3250_pdma1_peri);
exynos_pdma1_pdata.peri_id = exynos3250_pdma1_peri;
}
if (soc_is_exynos4210() || soc_is_exynos4212() ||
soc_is_exynos4412() || soc_is_exynos3470()) {
exynos_pdma0_device.res.start = EXYNOS4_PA_PDMA0;
exynos_pdma0_device.res.end = EXYNOS4_PA_PDMA0 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS4_IRQ_PDMA0;
exynos_pdma1_device.res.start = EXYNOS4_PA_PDMA1;
exynos_pdma1_device.res.end = EXYNOS4_PA_PDMA1 + SZ_4K;
exynos_pdma1_device.irq[0] = EXYNOS4_IRQ_PDMA1;
exynos_mdma_device.res.start = EXYNOS4_PA_MDMA1;
exynos_mdma_device.res.end = EXYNOS4_PA_MDMA1 + SZ_4K;
exynos_mdma_device.irq[0] = EXYNOS4_IRQ_MDMA1;
} else if (soc_is_exynos5410() || soc_is_exynos5420()) {
exynos_mdma_device.res.start = EXYNOS5_PA_MDMA0;
exynos_mdma_device.res.end = EXYNOS5_PA_MDMA0 + SZ_4K;
exynos_mdma_device.irq[0] = EXYNOS5_IRQ_MDMA0;
} else if (soc_is_exynos5260()) {
exynos5260_pdma0_device.res.start = EXYNOS5260_PA_PDMA0;
exynos5260_pdma0_device.res.end = EXYNOS5260_PA_PDMA0 + SZ_4K;
exynos5260_pdma0_device.irq[0] = EXYNOS5260_IRQ_PDMA0;
exynos5260_mdma_device.res.start = EXYNOS5260_PA_NS_MDMA0;
exynos5260_mdma_device.res.end = EXYNOS5260_PA_NS_MDMA0 + SZ_4K;
exynos5260_mdma_device.irq[0] = EXYNOS5260_IRQ_MDMA_1;
exynos5260_adma_device.res.start = EXYNOS5260_PA_ADMA0;
exynos5260_adma_device.res.end = EXYNOS5260_PA_ADMA0 + SZ_4K;
exynos5260_adma_device.irq[0] = EXYNOS5260_IRQ_ADMA;
} else if (soc_is_exynos4415()) {
exynos_pdma0_device.res.start = EXYNOS4_PA_PDMA0;
exynos_pdma0_device.res.end = EXYNOS4_PA_PDMA0 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS4_IRQ_PDMA0;
exynos_pdma1_device.res.start = EXYNOS4_PA_PDMA1;
exynos_pdma1_device.res.end = EXYNOS4_PA_PDMA1 + SZ_4K;
exynos_pdma1_device.irq[0] = EXYNOS4_IRQ_PDMA1;
exynos_mdma_device.res.start = EXYNOS4_PA_MDMA1;
exynos_mdma_device.res.end = EXYNOS4_PA_MDMA1 + SZ_4K;
exynos_mdma_device.irq[0] = EXYNOS4_IRQ_MDMA1;
} else if (soc_is_exynos3250()) {
exynos_pdma0_device.res.start = EXYNOS3_PA_PDMA0;
exynos_pdma0_device.res.end = EXYNOS3_PA_PDMA0 + SZ_4K;
exynos_pdma0_device.irq[0] = EXYNOS3_IRQ_PDMA0;
exynos_pdma1_device.res.start = EXYNOS3_PA_PDMA1;
exynos_pdma1_device.res.end = EXYNOS3_PA_PDMA1 + SZ_4K;
exynos_pdma1_device.irq[0] = EXYNOS3_IRQ_PDMA1;
}
if (soc_is_exynos5260()) {
dma_cap_set(DMA_SLAVE, exynos5260_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos5260_pdma0_pdata.cap_mask);
amba_device_register(&exynos5260_pdma0_device, &iomem_resource);
dma_cap_set(DMA_MEMCPY, exynos5260_mdma_pdata.cap_mask);
amba_device_register(&exynos5260_mdma_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos5260_adma_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos5260_adma_pdata.cap_mask);
amba_device_register(&exynos5260_adma_device, &iomem_resource);
} else if (soc_is_exynos3250()) {
dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
amba_device_register(&exynos_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
amba_device_register(&exynos_pdma1_device, &iomem_resource);
} else {
dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
amba_device_register(&exynos_pdma0_device, &iomem_resource);
dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
amba_device_register(&exynos_pdma1_device, &iomem_resource);
dma_cap_set(DMA_MEMCPY, exynos_mdma_pdata.cap_mask);
amba_device_register(&exynos_mdma_device, &iomem_resource);
}
if (soc_is_exynos5420()) {
dma_cap_set(DMA_SLAVE, exynos_adma0_pdata.cap_mask);
dma_cap_set(DMA_CYCLIC, exynos_adma0_pdata.cap_mask);
amba_device_register(&exynos_adma0_device, &iomem_resource);
}
return 0;
}
static void exynos_sfr_restore(unsigned int i)
{
struct dw_mci *host = dw_mci_lpa_host[i];
int startbit_clear = false;
unsigned int cmd_status = 0;
unsigned long timeout = jiffies + msecs_to_jiffies(500);
/*
* To update clock configurations, CIU should be enabled.
*/
spin_lock(&host->cclk_lock);
dw_mci_ciu_clk_en(host);
spin_unlock(&host->cclk_lock);
__raw_writel(dw_mci_save_sfr[i][0], host->regs + DWMCI_CTRL);
__raw_writel(dw_mci_save_sfr[i][1], host->regs + DWMCI_PWREN);
__raw_writel(dw_mci_save_sfr[i][2], host->regs + DWMCI_CLKDIV);
__raw_writel(dw_mci_save_sfr[i][3], host->regs + DWMCI_CLKSRC);
__raw_writel(dw_mci_save_sfr[i][4], host->regs + DWMCI_CLKENA);
__raw_writel(dw_mci_save_sfr[i][5], host->regs + DWMCI_TMOUT);
__raw_writel(dw_mci_save_sfr[i][6], host->regs + DWMCI_CTYPE);
__raw_writel(dw_mci_save_sfr[i][7], host->regs + DWMCI_INTMASK);
__raw_writel(dw_mci_save_sfr[i][8], host->regs + DWMCI_FIFOTH);
__raw_writel(dw_mci_save_sfr[i][9], host->regs + DWMCI_UHS_REG);
__raw_writel(dw_mci_save_sfr[i][10], host->regs + DWMCI_BMOD);
__raw_writel(dw_mci_save_sfr[i][11], host->regs + DWMCI_PLDMND);
__raw_writel(dw_mci_save_sfr[i][12], host->regs + DWMCI_DBADDR);
__raw_writel(dw_mci_save_sfr[i][13], host->regs + DWMCI_IDINTEN);
__raw_writel(dw_mci_save_sfr[i][14], host->regs + DWMCI_CLKSEL);
__raw_writel(dw_mci_save_sfr[i][15], host->regs + DWMCI_CDTHRCTL);
if (soc_is_exynos3250() || soc_is_exynos4415() ||
soc_is_exynos5420() || soc_is_exynos5260() || soc_is_exynos3470()) {
__raw_writel(dw_mci_save_sfr[i][16], host->regs +
DWMCI_DDR200_RDDQS_EN + 0x70);
__raw_writel(dw_mci_save_sfr[i][17], host->regs +
DWMCI_DDR200_DLINE_CTRL + 0x70);
} else {
__raw_writel(dw_mci_save_sfr[i][16], host->regs +
DWMCI_DDR200_RDDQS_EN);
__raw_writel(dw_mci_save_sfr[i][17], host->regs +
DWMCI_DDR200_DLINE_CTRL);
}
__raw_writel(0, host->regs + DWMCI_CMDARG);
wmb();
#ifdef CONFIG_BCM4334
if (i == 1)
return;
#endif
__raw_writel((DWMCI_CMD_START | DWMCI_CMD_UPD_CLK | DWMCI_CMD_PRV_DAT_WAIT),
host->regs + DWMCI_CMD);
while (time_before(jiffies, timeout)) {
cmd_status = __raw_readl(host->regs + DWMCI_CMD);
if (!(cmd_status & DWMCI_CMD_START)) {
startbit_clear = true;
return;
}
}
if (startbit_clear == false)
dev_err(&host->dev, "CMD start bit stuck %02d\n", i);
}
static int exynos_power_up_cpu(unsigned int cpu)
{
unsigned int timeout;
unsigned int val;
unsigned int tmp;
void __iomem *power_base;
power_base = cpu_boot_info[cpu].power_base;
if (power_base == 0)
return -EPERM;
val = __raw_readl(power_base + 0x4);
if (!(val & EXYNOS_CORE_LOCAL_PWR_EN)) {
tmp = __raw_readl(power_base);
tmp |= (EXYNOS_CORE_LOCAL_PWR_EN);
tmp |= (EXYNOS_CORE_AUTOWAKEUP_EN);
__raw_writel(tmp, power_base);
/* wait max 10 ms until cpu is on */
timeout = 10;
while (timeout) {
val = __raw_readl(power_base + 0x4);
if ((val & EXYNOS_CORE_LOCAL_PWR_EN) ==
EXYNOS_CORE_LOCAL_PWR_EN)
break;
/* HACK for TRUSTZONE: After Bootup, the hotplug out works but while
* hotplugging in we have to write twice to power_base reg
*/
#if defined(CONFIG_SOC_EXYNOS4415) && defined(CONFIG_ARM_TRUSTZONE)
__raw_writel(tmp, power_base);
#endif
mdelay(1);
timeout--;
}
if (timeout == 0) {
printk(KERN_ERR "cpu%d power up failed", cpu);
return -ETIMEDOUT;
}
}
#if !defined(CONFIG_MACH_GARDA)
/*
* Check Power down cpu wait on WFE, and occur SW reset
*/
if (soc_is_exynos3470() || soc_is_exynos3250()) {
while(!__raw_readl(EXYNOS_PMUREG(0x0908)))
udelay(10);
udelay(10);
tmp = __raw_readl(power_base + 0x4);
tmp |= (0x3 << 8);
__raw_writel(tmp, power_base + 0x4);
/* TODO set COREX's WAKEUP_FROM_LOCAL_CFG register with 0x3 */
printk("cpu%d: SWRESET\n", cpu);
__raw_writel(((1 << 4) << cpu), EXYNOS_PMUREG(0x0400));
}
#endif
return 0;
}
static void exynos_dwmci_set_io_timing(void *data, unsigned int tuning,
unsigned char timing, struct mmc_host *mmc)
{
struct dw_mci *host = (struct dw_mci *)data;
struct dw_mci_board *pdata = host->pdata;
struct dw_mci_clk *clk_tbl = pdata->clk_tbl;
u32 clksel, rddqs, dline;
u32 sclkin, cclkin;
unsigned char timing_init = MMC_TIMING_INIT;
if (timing > MMC_TIMING_MMC_HS200_DDR) {
pr_err("%s: timing(%d): not suppored\n", __func__, timing);
return;
}
sclkin = clk_tbl[timing].sclkin;
cclkin = clk_tbl[timing].cclkin;
if (timing == MMC_TIMING_LEGACY &&
pdata->misc_flag & DW_MMC_MISC_LOW_FREQ_HOOK) {
if (mmc == NULL || (mmc && mmc->ios.clock <= mmc->f_init)) {
sclkin = clk_tbl[timing_init].sclkin;
cclkin = clk_tbl[timing_init].cclkin;
}
}
rddqs = DWMCI_DDR200_RDDQS_EN_DEF;
dline = DWMCI_DDR200_DLINE_CTRL_DEF;
clksel = __raw_readl(host->regs + DWMCI_CLKSEL);
if (host->bus_hz != cclkin) {
host->bus_hz = cclkin;
host->current_speed = 0;
if (host->cclk2)
clk_set_rate(host->cclk2, sclkin);
clk_set_rate(host->cclk, sclkin);
}
if (timing == MMC_TIMING_MMC_HS200_DDR) {
clksel = (pdata->ddr200_timing & 0xfffffff8) | pdata->clk_smpl;
if (pdata->is_fine_tuned)
clksel |= BIT(6);
if (!tuning) {
rddqs |= DWMCI_RDDQS_EN;
if (host->pdata->delay_line)
dline = DWMCI_FIFO_CLK_DELAY_CTRL(0x2) |
DWMCI_RD_DQS_DELAY_CTRL(host->pdata->delay_line);
else
dline = DWMCI_FIFO_CLK_DELAY_CTRL(0x2) |
DWMCI_RD_DQS_DELAY_CTRL(90);
host->quirks &= ~DW_MCI_QUIRK_NO_DETECT_EBIT;
}
} else if (timing == MMC_TIMING_MMC_HS200 ||
timing == MMC_TIMING_UHS_SDR104) {
clksel = (clksel & 0xfff8ffff) | (pdata->clk_drv << 16);
} else if (timing == MMC_TIMING_UHS_SDR50) {
clksel = (clksel & 0xfff8ffff) | (pdata->clk_drv << 16);
} else if (timing == MMC_TIMING_UHS_DDR50) {
clksel = pdata->ddr_timing;
} else {
clksel = pdata->sdr_timing;
}
__raw_writel(clksel, host->regs + DWMCI_CLKSEL);
if (soc_is_exynos3250() || soc_is_exynos4415() ||
soc_is_exynos5420() || soc_is_exynos5260() || soc_is_exynos3470()) {
__raw_writel(rddqs, host->regs + DWMCI_DDR200_RDDQS_EN + 0x70);
__raw_writel(dline, host->regs + DWMCI_DDR200_DLINE_CTRL + 0x70);
if (timing == MMC_TIMING_MMC_HS200_DDR)
__raw_writel(0x1, host->regs + DWMCI_DDR200_ASYNC_FIFO_CTRL + 0x70);
} else {
__raw_writel(rddqs, host->regs + DWMCI_DDR200_RDDQS_EN);
__raw_writel(dline, host->regs + DWMCI_DDR200_DLINE_CTRL);
if (timing == MMC_TIMING_MMC_HS200_DDR)
__raw_writel(0x1, host->regs + DWMCI_DDR200_ASYNC_FIFO_CTRL);
}
}
static int exynos_power_up_cpu(unsigned int cpu)
{
unsigned int timeout;
unsigned int val;
void __iomem *power_base;
#ifndef CONFIG_EXYNOS5_MP
unsigned int cluster = (read_cpuid_mpidr() >> 8) & 0xf;
#endif
unsigned int lpe_bits, lpe_bits_status, enabled = 0;
power_base = cpu_boot_info[cpu].power_base;
if (power_base == 0)
return -EPERM;
val = __raw_readl(power_base + 0x4);
if (soc_is_exynos5260()) {
if (val & 0x40000)
enabled = 1;
else {
val = __raw_readl(power_base + 0x8);
if (val & EXYNOS5_USE_SC_COUNTER) {
val &= ~EXYNOS5_USE_SC_COUNTER;
val |= EXYNOS5_USE_SC_FEEDBACK;
__raw_writel(val, power_base + 0x8);
}
lpe_bits = 0x000F000F;
lpe_bits_status = 0x4000F;
#ifndef CONFIG_ARM_TRUSTZONE
__raw_writel(0, cpu_boot_info[cpu].boot_base);
#endif
}
} else {
if (val & EXYNOS_CORE_LOCAL_PWR_EN)
enabled = 1;
else {
lpe_bits = EXYNOS_CORE_LOCAL_PWR_EN;
lpe_bits_status = EXYNOS_CORE_LOCAL_PWR_EN;
}
}
if (!enabled) {
__raw_writel(lpe_bits, power_base);
/* wait max 10 ms until cpu is on */
timeout = 10;
while (timeout) {
val = __raw_readl(power_base + 0x4);
if ((val & lpe_bits) ==
lpe_bits_status)
break;
mdelay(1);
timeout--;
}
if (timeout == 0) {
printk(KERN_ERR "cpu%d power up failed", cpu);
return -ETIMEDOUT;
}
}
#ifdef CONFIG_EXYNOS5_MP
if (cpu < 4) {
#else
if (cluster) {
#endif
while(!__raw_readl(EXYNOS_PMU_SPARE2))
udelay(10);
udelay(10);
if (soc_is_exynos5260()) {
val = __raw_readl(power_base + 0x4);
val |= (0xf << 8);
__raw_writel(val, power_base + 0x4);
pr_debug("cpu%d: SWRESEET\n", cpu);
__raw_writel((0x1 << 1), power_base + 0xc);
} else {
printk(KERN_DEBUG "cpu%d: SWRESET\n", cpu);
val = ((1 << 20) | (1 << 8)) << cpu;
__raw_writel(val, EXYNOS_SWRESET);
}
}
return 0;
}
#else
#error "exynos_power_up_cpu() does not defined"
#endif
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
int ret;
/*
* Set synchronisation state between this boot processor
* and the secondary one
*/
spin_lock(&boot_lock);
#ifdef CONFIG_WATCHDOG
if (soc_is_exynos5250())
watchdog_save();
#endif
#ifdef CONFIG_SOC_EXYNOS4415
__raw_writel(0x0, cpu_boot_info[cpu].boot_base);
#endif
ret = exynos_power_up_cpu(cpu);
if (ret) {
spin_unlock(&boot_lock);
return ret;
}
/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
*
* Note that "pen_release" is the hardware CPU ID, whereas
* "cpu" is Linux's internal ID.
*/
write_pen_release(cpu_logical_map(cpu));
/*
* Send the secondary CPU a soft interrupt, thereby causing
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
#ifdef CONFIG_ARM_TRUSTZONE
if (soc_is_exynos4210() || soc_is_exynos4212() ||
soc_is_exynos5250())
exynos_smc(SMC_CMD_CPU1BOOT, 0, 0, 0);
else if (soc_is_exynos4412() || soc_is_exynos4415())
exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
#endif
__raw_writel(virt_to_phys(exynos4_secondary_startup),
cpu_boot_info[cpu].boot_base);
#ifdef CONFIG_WATCHDOG
if (soc_is_exynos5250())
watchdog_restore();
#endif
if (soc_is_exynos3250() || soc_is_exynos3470() ||
soc_is_exynos5410() || soc_is_exynos5420() ||
soc_is_exynos5260())
dsb_sev();
else
arm_send_ping_ipi(cpu);
if (pen_release == -1)
break;
udelay(10);
}
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
