extern void
socle_scu_wdt_reset_enable(int en)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_DEVCON) ;
if(en == 1)
tmp &= ~ SCU_DEVCON_WDT_RST;
else
tmp |= SCU_DEVCON_WDT_RST;
socle_scu_write(tmp, SOCLE_SCU_DEVCON);
}
/* PLL lock period */
extern void
socle_scu_pll_lock_period_set (int period)
{
u32 tmp;
if(period < 2)
period = 2;
tmp = socle_scu_read(SOCLE_SCU_MCLKDIV) & ~SCU_MCLKDIV_PLL_LOCK_PERIOD_M;
tmp = tmp | period;
socle_scu_write(tmp, SOCLE_SCU_MCLKDIV);
return ;
}
extern void
socle_scu_adc_clk_div_set (int div)
{
u32 tmp;
if(div < 2)
div = 2;
tmp = socle_scu_read(SOCLE_SCU_MCLKDIV) & ~SCU_MCLKDIV_ADC_CLK_DIV_M;
tmp = tmp | div;
socle_scu_write(tmp, SOCLE_SCU_MCLKDIV);
return ;
}
extern void
socle_scu_nfiq_polarity_high(int en)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_DEVCON) ;
if(en == 1)
tmp |= SCU_DEVCON_FIQ_POLAR_HIGH;
else
tmp &= ~SCU_DEVCON_FIQ_POLAR_HIGH;
socle_scu_write(tmp, SOCLE_SCU_DEVCON);
}
/* slow mode -- systen clock */
extern void
socle_scu_slow_mode_disable (int i)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_PWMCON);
if(i == 1)
socle_scu_write(tmp & ~SCU_PWMCON_PWR_NOR, SOCLE_SCU_PWMCON);
else
socle_scu_write(tmp | SCU_PWMCON_PWR_NOR, SOCLE_SCU_PWMCON);
return ;
}
/* stop mode -- systen clock */
extern void
socle_scu_stop_mode_enable (int i)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_PWMCON);
if(i == 1)
socle_scu_write(tmp | SCU_PWMCON_PWR_STOP , SOCLE_SCU_PWMCON);
else
socle_scu_write(tmp & ~SCU_PWMCON_PWR_STOP , SOCLE_SCU_PWMCON);
return ;
}
/* Stand by wait for interrupt */
extern void
socle_scu_pw_standbywfi_enable (int i)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_PWMCON);
if(i ==1)
socle_scu_write(tmp | SCU_PWMCON_STANDBYWFI , SOCLE_SCU_PWMCON);
else
socle_scu_write(tmp & ~SCU_PWMCON_STANDBYWFI , SOCLE_SCU_PWMCON);
return ;
}
extern unsigned long __init
get_pll_clock(void)
{
unsigned long scu_clock, scu_ratio, scu_n, scu_m, scu_od, normal,tmp;
/* get PLL clock */
normal = socle_scu_read(CHEETAH_SCU_PWMCON);
if(normal & 0x1)
{
tmp = socle_scu_read(CHEETAH_SCU_MPLLCON);
scu_n = (tmp & SCU_MPLLCON_N) >> SCU_MPLLCON_N_S;
scu_m = (tmp & SCU_MPLLCON_M) >> SCU_MPLLCON_M_S;
scu_od = (tmp & SCU_MPLLCON_OD) >> SCU_MPLLCON_OD_S;
if(scu_od == 0)
scu_od = 1;
else if (scu_od == 1)
scu_od = 2;
else if (scu_od == 2)
scu_od = 4;
else
scu_od = 8;
scu_clock = SCU_XIN * scu_m / scu_n / scu_od;
}
extern u32
socle_scu_mpll_clock_get (void)
{
u32 m,n,od;
u32 mclk;
mclk = socle_scu_read(SOCLE_SCU_MPLLCON);
n = (mclk & SCU_MPLLCON_N_MASK) >> SCU_MPLLCON_N;
m = (mclk & SCU_MPLLCON_M_MASK) >> SCU_MPLLCON_M;
od = (mclk & SCU_MPLLCON_OD_MASK) >> SCU_MPLLCON_OD;
mclk = socle_scu_pll_formula(m, n, od, MPLL_XIN);
return mclk;
}
extern void
socle_scu_sw_reset_enable(int en)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_DEVCON) ;
if(en == 1)
tmp &= ~SCU_DEVCON_SW_RST;
else
tmp |= SCU_DEVCON_SW_RST;
SCUDBUG("SCU_DEVCON_SW_RST = 0x%08x, tmp = 0x%08x\n", SCU_DEVCON_SW_RST, tmp);
socle_scu_write(tmp, SOCLE_SCU_DEVCON);
}
extern int
socle_scu_upll_get (void)
{
int m,n,od;
u32 uclk;
uclk = socle_scu_read(SOCLE_SCU_UPLLCON);
n = (uclk & SCU_UPLLCON_N_MASK) >> SCU_UPLLCON_N;
m = (uclk & SCU_UPLLCON_M_MASK) >>SCU_UPLLCON_M;
od = (uclk & SCU_UPLLCON_OD_MASK) >> SCU_UPLLCON_OD;
uclk = socle_scu_pll_formula(m, n, od,UPLL_XIN);
return uclk;
}
extern int
socle_scu_hardmacro_chip_stop_mode_no_pwr_control (int chip)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_ACLKEN);
switch(chip){
case SOCLE_SCU_SDC_HARDMACRO :
tmp = tmp & ~SCU_ACLK_SDC_HARDMACRO;
break;
case SOCLE_SCU_MAC_HARDMACRO :
tmp = tmp & ~SCU_ACLK_MAC_HARDMACRO;
break;
case SOCLE_SCU_LCDC_HARDMACRO :
tmp = tmp & ~SCU_ACLK_LCDC_HARDMACRO;
break;
case SOCLE_SCU_OTG0_HARDMACRO :
tmp = tmp & ~SCU_ACLK_OTG0_HARDMACRO;
break;
case SOCLE_SCU_OTG1_HARDMACRO :
tmp = tmp & ~SCU_ACLK_OTG1_HARDMACRO;
break;
case SOCLE_SCU_NFC_HARDMACRO :
tmp = tmp & ~SCU_ACLK_NFC_HARDMACRO;
break;
case SOCLE_SCU_VIP_HARDMACRO :
tmp = tmp & ~SCU_ACLK_VIP_HARDMACRO;
break;
case SOCLE_SCU_VOP_HARDMACRO :
tmp = tmp & ~SCU_ACLK_VOP_HARDMACRO;
break;
default :
SCUMSG("unknow chip number\n");
return -1;
break;
}
socle_scu_write(tmp, SOCLE_SCU_ACLKEN);
return 0;
}
/* UPLL configuration */
extern int
socle_scu_upll_set (int clock)
{
u32 tmp, upll;
switch(clock){
case SOCLE_SCU_UART_CLOCK_176:
tmp = SCU_UART_CLOCK_176;
break;
default :
socle_scu_show("unknow upll clock !!\n");
return -1;
break;
}
upll = ((socle_scu_read(SOCLE_SCU_UPLLCON) & ~SCU_UPLLCON_PLL_MASK) | (tmp ));
socle_scu_write(upll, SOCLE_SCU_UPLLCON);
return 0;
}
extern int
socle_scu_uart_clk_get (int uart)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_MCLKDIV);
switch(uart){
case 0 :
tmp = (tmp & SCU_MCLKDIV_UART0_CLK_M) >> SCU_MCLKDIV_UART0_CLK_S;
break;
case 1:
tmp = (tmp & SCU_MCLKDIV_UART1_CLK_M) >> SCU_MCLKDIV_UART1_CLK_S;
break;
case 2:
tmp = (tmp & SCU_MCLKDIV_UART2_CLK_M) >> SCU_MCLKDIV_UART2_CLK_S;
break;
default :
socle_scu_show("unknow UART index\n");
return -1;
break;
}
switch(tmp){
case SCU_MCLKDIV_UART_CLK_24:
tmp = SOCLE_SCU_UART_CLK_24;
break;
case SCU_MCLKDIV_UART_CLK_UPLL:
tmp = SOCLE_SCU_UART_CLK_UPLL;
break;
case SCU_MCLKDIV_UART_CLK_UPLL_2:
tmp = SOCLE_SCU_UART_CLK_UPLL_2;
break;
case SCU_MCLKDIV_UART_CLK_UPLL_4:
tmp = SOCLE_SCU_UART_CLK_UPLL_4;
break;
}
return tmp;
}
/* CPU/AHB clock ratio */
extern int
socle_scu_clock_ratio_set (int ratio)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_MCLKDIV) & ~SCU_MCLKDIV_CLK_RATIO_MASK;
switch(ratio){
case SOCLE_SCU_CLOCK_RATIO_1_1 :
//printf("set ratio 1:1\n");
printf(" ");
tmp = tmp |SCU_MCLKDIV_CLK_RATIO_1_1;
break;
case SOCLE_SCU_CLOCK_RATIO_2_1 :
//printf("set ratio 2:1\n");
printf(" ");
tmp = tmp |SCU_MCLKDIV_CLK_RATIO_2_1;
break;
case SOCLE_SCU_CLOCK_RATIO_3_1 :
//printf("set ratio 3:1\n");
printf(" ");
tmp = tmp |SCU_MCLKDIV_CLK_RATIO_3_1;
break;
case SOCLE_SCU_CLOCK_RATIO_4_1 :
//printf("set ratio 4:1\n");
printf(" ");
tmp = tmp |SCU_MCLKDIV_CLK_RATIO_4_1;
break;
default :
socle_scu_show("unknow ratio value\n");
return -1;
break;
}
//printf("ratio2\n");
socle_scu_write(tmp, SOCLE_SCU_MCLKDIV);
printf("\n");
return 0;
}
/* Boot source selection status */
extern int
socle_scu_boot_source_status (void)
{
u32 tmp, status;
tmp = socle_scu_read(SOCLE_SCU_PWMCON) & SCU_PWMCON_BOOT_MODE;
switch(tmp){
case SCU_PWMCON_BOOT_MODE_NOR_16 :
status = SOCLE_SCU_BOOT_NOR_16;
break;
case SCU_PWMCON_BOOT_MODE_NOR_8 :
status = SOCLE_SCU_BOOT_NOR_8;
break;
case SCU_PWMCON_BOOT_MODE_NAND :
status = SOCLE_SCU_BOOT_NAND;
break;
case SCU_PWMCON_BOOT_MODE_ISP:
status = SOCLE_SCU_BOOT_ISP_ROM;
break;
}
return status;
}
/* aclk enable/disable */
extern int
socle_scu_aclk_enable (int aclk, int en)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_ACLKEN);
if(en){
switch(aclk){
case SOCLE_SCU_ACLK_SD_CLKOUT_FOR_STSDR :
tmp = tmp | SCU_ACLK_ST_SDR;
break;
case SOCLE_SCU_ACLK_LCDCLK_VOPPCLK_FOR_LCDC_VOP :
tmp = tmp | SCU_ACLK_LCD_VOP;
break;
case SOCLE_SCU_ACLK_RMIICLK_FOR_MAC :
tmp = tmp | SCU_ACLK_MAC;
break;
case SOCLE_SCU_ACLK_VIP :
tmp = tmp | SCU_ACLK_VIP;
break;
case SOCLE_SCU_ACLK_UART :
tmp = tmp | SCU_ACLK_UART;
break;
case SOCLE_SCU_ACLK_UTMICLK_FOR_OTG0 :
tmp = tmp | SCU_ACLK_UTMI_OTG0;
break;
case SOCLE_SCU_ACLK_UTMICLK_FOR_OTG1 :
tmp = tmp | SCU_ACLK_UTMI_OTG1;
break;
case SOCLE_SCU_ACLK_ADCCLK_FOR_ADC :
tmp = tmp | SCU_ACLK_ADC;
break;
case SOCLE_SCU_ACLK_I2SCLK_FOR_I2S :
tmp = tmp | SCU_ACLK_I2S;
break;
case SOCLE_SCU_ACLK_UCLK_FOR_UART2 :
tmp = tmp | SCU_ACLK_UART2;
break;
case SOCLE_SCU_ACLK_UCLK_FOR_UART1 :
tmp = tmp | SCU_ACLK_UART1;
break;
case SOCLE_SCU_ACLK_UCLK_FOR_UART0 :
tmp = tmp | SCU_ACLK_UART0;
break;
default :
SCUMSG("unknow IP number\n");
return -1;
break;
}
}else{
switch(aclk){
case SOCLE_SCU_ACLK_SD_CLKOUT_FOR_STSDR :
tmp = tmp & ~SCU_ACLK_ST_SDR;
break;
case SOCLE_SCU_ACLK_LCDCLK_VOPPCLK_FOR_LCDC_VOP :
tmp = tmp & ~SCU_ACLK_LCD_VOP;
break;
case SOCLE_SCU_ACLK_RMIICLK_FOR_MAC :
tmp = tmp & ~SCU_ACLK_MAC;
break;
case SOCLE_SCU_ACLK_VIP :
tmp = tmp & ~SCU_ACLK_VIP;
break;
case SOCLE_SCU_ACLK_UART :
tmp = tmp & ~SCU_ACLK_UART;
break;
case SOCLE_SCU_ACLK_UTMICLK_FOR_OTG0 :
tmp = tmp & ~SCU_ACLK_UTMI_OTG0;
break;
case SOCLE_SCU_ACLK_UTMICLK_FOR_OTG1 :
tmp = tmp & ~SCU_ACLK_UTMI_OTG1;
break;
case SOCLE_SCU_ACLK_ADCCLK_FOR_ADC :
tmp = tmp & ~SCU_ACLK_ADC;
break;
case SOCLE_SCU_ACLK_I2SCLK_FOR_I2S :
tmp = tmp & ~SCU_ACLK_I2S;
break;
case SOCLE_SCU_ACLK_UCLK_FOR_UART2 :
tmp = tmp & ~SCU_ACLK_UART2;
break;
case SOCLE_SCU_ACLK_UCLK_FOR_UART1 :
tmp = tmp & ~SCU_ACLK_UART1;
break;
case SOCLE_SCU_ACLK_UCLK_FOR_UART0 :
tmp = tmp & ~SCU_ACLK_UART0;
break;
default :
SCUMSG("unknow IP number\n");
return -1;
break;
}
}
socle_scu_write(tmp, SOCLE_SCU_ACLKEN);
return 0;
}
extern int
socle_scu_aclk_disable (int ip)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_ACLKEN);
switch(ip){
case SOCLE_SCU_ACLK_SDC_HARDMACRO :
tmp = tmp & ~SCU_ACLK_SDC_HARDMACRO;
break;
case SOCLE_SCU_ACLK_MAC_HARDMACRO :
tmp = tmp & ~SCU_ACLK_MAC_HARDMACRO;
break;
case SOCLE_SCU_ACLK_LCDC_HARDMACRO :
tmp = tmp & ~SCU_ACLK_LCDC_HARDMACRO;
break;
case SOCLE_SCU_ACLK_UDC_HARDMACRO :
tmp = tmp & ~SCU_ACLK_UDC_HARDMACRO;
break;
case SOCLE_SCU_ACLK_MPLL_OSC_CRYSTAL :
tmp = tmp & ~SCU_ACLK_MPLL_OSC_CRYSTAL;
break;
case SOCLE_SCU_ACLK_MPLL_OSC_CLK :
tmp = tmp & ~SCU_ACLK_MPLL_OSC_CLK;
break;
case SOCLE_SCU_ACLK_ST_SDR :
tmp = tmp & ~SCU_ACLK_ST_SDR;
break;
case SOCLE_SCU_ACLK_HS_UART :
tmp = tmp & ~SCU_ACLK_HS_UART;
break;
case SOCLE_SCU_ACLK_LCD_VOP :
tmp = tmp & ~SCU_ACLK_LCD_VOP;
break;
case SOCLE_SCU_ACLK_MAC :
tmp = tmp & ~SCU_ACLK_MAC;
break;
case SOCLE_SCU_ACLK_UHC0 :
tmp = tmp & ~SCU_ACLK_UHC0;
break;
case SOCLE_SCU_ACLK_UHC1 :
tmp = tmp & ~SCU_ACLK_UHC1;
break;
case SOCLE_SCU_ACLK_UTMI_UHC1 :
tmp = tmp & ~SCU_ACLK_UTMI_UHC1;
break;
case SOCLE_SCU_ACLK_UTMI_UHC0 :
tmp = tmp & ~SCU_ACLK_UTMI_UHC0;
break;
case SOCLE_SCU_ACLK_UDC :
tmp = tmp & ~SCU_ACLK_UDC;
break;
case SOCLE_SCU_ACLK_ADC :
tmp = tmp & ~SCU_ACLK_ADC;
break;
case SOCLE_SCU_ACLK_I2S :
tmp = tmp & ~SCU_ACLK_I2S;
break;
case SOCLE_SCU_ACLK_UART2 :
tmp = tmp & ~SCU_ACLK_UART2;
break;
case SOCLE_SCU_ACLK_UART1 :
tmp = tmp & ~SCU_ACLK_UART1;
break;
case SOCLE_SCU_ACLK_UART0 :
tmp = tmp & ~SCU_ACLK_UART0;
break;
default :
socle_scu_show("unknow IP number\n");
return -1;
break;
}
socle_scu_write(tmp, SOCLE_SCU_ACLKEN);
return 0;
}
extern int
socle_scu_mclk_disable (int ip)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_MCLKEN);
switch(ip){
case SOCLE_SCU_MCLK_DCM :
tmp = tmp & ~SCU_MCLK_DCM;
break;
case SOCLE_SCU_MCLK_STSDR :
tmp = tmp & ~SCU_MCLK_STSDR;
break;
case SOCLE_SCU_MCLK_NFC :
tmp = tmp & ~SCU_MCLK_NFC;
break;
case SOCLE_SCU_MCLK_HDMA :
tmp = tmp & ~SCU_MCLK_HDMA;
break;
case SOCLE_SCU_MCLK_VOP :
tmp = tmp & ~SCU_MCLK_VOP;
break;
case SOCLE_SCU_MCLK_UHC0 :
tmp = tmp & ~SCU_MCLK_UHC0;
break;
case SOCLE_SCU_MCLK_UDC :
tmp = tmp & ~SCU_MCLK_UDC;
break;
case SOCLE_SCU_MCLK_UHC1 :
tmp = tmp & ~SCU_MCLK_UHC1;
break;
case SOCLE_SCU_MCLK_MAC :
tmp = tmp & ~SCU_MCLK_MAC;
break;
case SOCLE_SCU_MCLK_CLCD :
tmp = tmp & ~SCU_MCLK_CLCD;
break;
case SOCLE_SCU_MCLK_GPIO3 :
tmp = tmp & ~SCU_MCLK_GPIO3;
break;
case SOCLE_SCU_MCLK_GPIO2 :
tmp = tmp & ~SCU_MCLK_GPIO2;
break;
case SOCLE_SCU_MCLK_GPIO1 :
tmp = tmp & ~SCU_MCLK_GPIO1;
break;
case SOCLE_SCU_MCLK_GPIO0 :
tmp = tmp & ~SCU_MCLK_GPIO0;
break;
case SOCLE_SCU_MCLK_ADC :
tmp = tmp & ~SCU_MCLK_ADC;
break;
case SOCLE_SCU_MCLK_PWM :
tmp = tmp & ~SCU_MCLK_PWM;
break;
case SOCLE_SCU_MCLK_WDT :
tmp = tmp & ~SCU_MCLK_WDT;
break;
case SOCLE_SCU_MCLK_RTC :
tmp = tmp & ~SCU_MCLK_RTC;
break;
case SOCLE_SCU_MCLK_TIMER :
tmp = tmp & ~SCU_MCLK_TIMER;
break;
case SOCLE_SCU_MCLK_SDMMC :
tmp = tmp & ~SCU_MCLK_SDMMC;
break;
case SOCLE_SCU_MCLK_I2S :
tmp = tmp & ~SCU_MCLK_I2S;
break;
case SOCLE_SCU_MCLK_I2C :
tmp = tmp & ~SCU_MCLK_I2C;
break;
case SOCLE_SCU_MCLK_SPI1 :
tmp = tmp & ~SCU_MCLK_SPI1;
break;
case SOCLE_SCU_MCLK_SPI0 :
tmp = tmp & ~SCU_MCLK_SPI0;
break;
case SOCLE_SCU_MCLK_UART2 :
tmp = tmp & ~SCU_MCLK_UART2;
break;
case SOCLE_SCU_MCLK_UART1 :
tmp = tmp & ~SCU_MCLK_UART1;
break;
case SOCLE_SCU_MCLK_UART0 :
tmp = tmp & ~SCU_MCLK_UART0;
break;
default :
socle_scu_show("unknow IP number\n");
return -1;
break;
}
socle_scu_write(tmp, SOCLE_SCU_MCLKEN);
return 0;
}
/* MPLL configuration */
extern int
socle_scu_mpll_set (int clock)
{
u32 tmp, mpll;
switch(clock){
case SOCLE_SCU_CPU_CLOCK_33 :
tmp = SCU_CPU_CLOCK_33;
break;
case SOCLE_SCU_CPU_CLOCK_66 :
tmp = SCU_CPU_CLOCK_66;
break;
case SOCLE_SCU_CPU_CLOCK_80 :
tmp = SCU_CPU_CLOCK_80;
break;
case SOCLE_SCU_CPU_CLOCK_100 :
tmp = SCU_CPU_CLOCK_100;
break;
case SOCLE_SCU_CPU_CLOCK_132 :
tmp = SCU_CPU_CLOCK_132;
break;
case SOCLE_SCU_CPU_CLOCK_133 :
tmp = SCU_CPU_CLOCK_133;
break;
case SOCLE_SCU_CPU_CLOCK_166 :
tmp = SCU_CPU_CLOCK_166;
break;
case SOCLE_SCU_CPU_CLOCK_200 :
tmp = SCU_CPU_CLOCK_200;
break;
case SOCLE_SCU_CPU_CLOCK_240 :
tmp = SCU_CPU_CLOCK_240;
break;
#if 0
case SOCLE_SCU_CPU_CLOCK_258 :
tmp = SCU_CPU_CLOCK_258;
break;
#else
case SOCLE_SCU_CPU_CLOCK_252 :
tmp = SCU_CPU_CLOCK_252;
break;
#endif
case SOCLE_SCU_CPU_CLOCK_264 :
tmp = SCU_CPU_CLOCK_264;
break;
case SOCLE_SCU_CPU_CLOCK_266 :
tmp = SCU_CPU_CLOCK_266;
break;
case SOCLE_SCU_CPU_CLOCK_280 :
tmp = SCU_CPU_CLOCK_280;
break;
case SOCLE_SCU_CPU_CLOCK_300 :
tmp = SCU_CPU_CLOCK_300;
break;
case SOCLE_SCU_CPU_CLOCK_320 :
tmp = SCU_CPU_CLOCK_320;
break;
case SOCLE_SCU_CPU_CLOCK_340 :
tmp = SCU_CPU_CLOCK_340;
break;
case SOCLE_SCU_CPU_CLOCK_350 :
tmp = SCU_CPU_CLOCK_350;
break;
case SOCLE_SCU_CPU_CLOCK_360 :
tmp = SCU_CPU_CLOCK_360;
break;
case SOCLE_SCU_CPU_CLOCK_400 :
tmp = SCU_CPU_CLOCK_400;
break;
default :
socle_scu_show("unknow upll clock !!\n");
return -1;
break;
}
mpll = ((socle_scu_read(SOCLE_SCU_MPLLCON) & ~SCU_MPLLCON_PLL_MASK) | (tmp ));
socle_scu_write(mpll, SOCLE_SCU_MPLLCON);
socle_get_cpu_clock();
return 0;
}
extern int
socle_scu_dev_disable(u32 dev)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_DEVCON) ;
switch(dev){
case SOCLE_DEVCON_NFC :
tmp = tmp & ~SCU_DEVCON_NFC_GPIO;
break;
case SOCLE_DEVCON_MAC :
tmp = tmp & ~SCU_DEVCON_MAC_GPIO;
break;
case SOCLE_DEVCON_TMR :
tmp = tmp & ~SCU_DEVCON_TMR_GPIO;
break;
case SOCLE_DEVCON_PWM0 :
tmp = tmp & ~SCU_DEVCON_PWM0_GPIO;
break;
case SOCLE_DEVCON_PWM1 :
tmp = tmp & ~SCU_DEVCON_PWM1_GPIO;
break;
case SOCLE_DEVCON_EXT_INT0 :
tmp = tmp & ~SCU_DEVCON_INT0;
break;
case SOCLE_DEVCON_EXT_INT0_NFIQ :
tmp = tmp & ~SCU_DEVCON_INT0;
break;
case SOCLE_DEVCON_EXT_INT1 :
tmp = tmp & ~SCU_DEVCON_INT1;
break;
case SOCLE_DEVCON_LCDC :
tmp = tmp & ~SCU_DEVCON_LCD_GPIO;
break;
case SOCLE_DEVCON_LCDC_VOP :
tmp = tmp & ~SCU_DEVCON_LCD_GPIO;
break;
case SOCLE_DEVCON_SPI0 :
tmp = tmp & ~SCU_DEVCON_SPI0_GPIO;
break;
case SOCLE_DEVCON_SPI1 :
tmp = tmp & ~SCU_DEVCON_SPI1_GPIO;
break;
case SOCLE_DEVCON_I2S_TX :
tmp = tmp & ~SCU_DEVCON_I2S_GPIO;
break;
case SOCLE_DEVCON_I2S_RX :
tmp = tmp & ~SCU_DEVCON_I2S_GPIO;
break;
case SOCLE_DEVCON_I2S_TX_RX :
tmp = tmp & ~SCU_DEVCON_I2S_GPIO;
break;
case SOCLE_DEVCON_I2C :
tmp = tmp & ~SCU_DEVCON_I2C_GPIO;
break;
case SOCLE_DEVCON_SDMMC :
tmp = tmp & ~SCU_DEVCON_SDMMC_GPIO;
break;
case SOCLE_DEVCON_UART0 :
tmp = tmp & ~SCU_DEVCON_UART0_GPIO;
break;
case SOCLE_DEVCON_UART1 :
tmp = tmp & ~SCU_DEVCON_UART1_GPIO;
break;
case SOCLE_DEVCON_UART2 :
tmp = tmp & ~SCU_DEVCON_UART2_GPIO;
break;
default :
socle_scu_show("unknow IP number\n");
return -1;
break;
}
socle_scu_write(tmp, SOCLE_SCU_DEVCON);
return 0;
}
/* hclk enable/disable */
extern int
socle_scu_hclk_enable (int hclk, int en)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_MCLKEN);
if(en){
switch(hclk){
case SOCLE_SCU_HCLK_ROM :
tmp = tmp | SCU_MCLK_ROM;
break;
case SOCLE_SCU_HCLK_DCM :
tmp = tmp | SCU_MCLK_DCM;
break;
case SOCLE_SCU_HCLK_STSDR :
tmp = tmp | SCU_MCLK_STSDR;
break;
case SOCLE_SCU_HCLK_NFC :
tmp = tmp | SCU_MCLK_NFC;
break;
case SOCLE_SCU_HCLK_HDMA :
tmp = tmp | SCU_MCLK_HDMA;
break;
case SOCLE_SCU_HCLK_VOP :
tmp = tmp | SCU_MCLK_VOP;
break;
case SOCLE_SCU_HCLK_VIP :
tmp = tmp | SCU_MCLK_VIP;
break;
case SOCLE_SCU_HCLK_OTG0 :
tmp = tmp | SCU_MCLK_OTG0;
break;
case SOCLE_SCU_HCLK_OTG1 :
tmp = tmp | SCU_MCLK_OTG1;
break;
case SOCLE_SCU_HCLK_MAC :
tmp = tmp | SCU_MCLK_MAC;
break;
case SOCLE_SCU_HCLK_CLCD :
tmp = tmp | SCU_MCLK_CLCD;
break;
default :
SCUMSG("unknow IP number\n");
return -1;
break;
}
}else{
switch(hclk){
case SOCLE_SCU_HCLK_ROM :
tmp = tmp & ~SCU_MCLK_ROM;
break;
case SOCLE_SCU_HCLK_DCM :
tmp = tmp & ~SCU_MCLK_DCM;
break;
case SOCLE_SCU_HCLK_STSDR :
tmp = tmp & ~SCU_MCLK_STSDR;
break;
case SOCLE_SCU_HCLK_NFC :
tmp = tmp & ~SCU_MCLK_NFC;
break;
case SOCLE_SCU_HCLK_HDMA :
tmp = tmp & ~SCU_MCLK_HDMA;
break;
case SOCLE_SCU_HCLK_VOP :
tmp = tmp & ~SCU_MCLK_VOP;
break;
case SOCLE_SCU_HCLK_VIP :
tmp = tmp & ~SCU_MCLK_VIP;
break;
case SOCLE_SCU_HCLK_OTG0 :
tmp = tmp & ~SCU_MCLK_OTG0;
break;
case SOCLE_SCU_HCLK_OTG1 :
tmp = tmp & ~SCU_MCLK_OTG1;
break;
case SOCLE_SCU_HCLK_MAC :
tmp = tmp & ~SCU_MCLK_MAC;
break;
case SOCLE_SCU_HCLK_CLCD :
tmp = tmp & ~SCU_MCLK_CLCD;
break;
default :
SCUMSG("unknow IP number\n");
return -1;
break;
}
}
socle_scu_write(tmp, SOCLE_SCU_MCLKEN);
return 0;
}
/* pclk enable/disable */
extern int
socle_scu_pclk_enable (int pclk, int en)
{
u32 tmp;
tmp = socle_scu_read(SOCLE_SCU_MCLKEN);
if(en){
switch(pclk){
case SOCLE_SCU_PCLK_GPIO3 :
tmp = tmp | SCU_MCLK_GPIO3;
break;
case SOCLE_SCU_PCLK_GPIO2 :
tmp = tmp | SCU_MCLK_GPIO2;
break;
case SOCLE_SCU_PCLK_GPIO1 :
tmp = tmp | SCU_MCLK_GPIO1;
break;
case SOCLE_SCU_PCLK_GPIO0 :
tmp = tmp | SCU_MCLK_GPIO0;
break;
case SOCLE_SCU_PCLK_ADC :
tmp = tmp | SCU_MCLK_ADC;
break;
case SOCLE_SCU_PCLK_PWM :
tmp = tmp | SCU_MCLK_PWM;
break;
case SOCLE_SCU_PCLK_WDT :
tmp = tmp | SCU_MCLK_WDT;
break;
case SOCLE_SCU_PCLK_RTC :
tmp = tmp | SCU_MCLK_RTC;
break;
case SOCLE_SCU_PCLK_TIMER :
tmp = tmp | SCU_MCLK_TIMER;
break;
case SOCLE_SCU_PCLK_SDMMC :
tmp = tmp | SCU_MCLK_SDMMC;
break;
case SOCLE_SCU_PCLK_I2S :
tmp = tmp | SCU_MCLK_I2S;
break;
case SOCLE_SCU_PCLK_I2C :
tmp = tmp | SCU_MCLK_I2C;
break;
case SOCLE_SCU_PCLK_SPI1 :
tmp = tmp | SCU_MCLK_SPI1;
break;
case SOCLE_SCU_PCLK_SPI0 :
tmp = tmp | SCU_MCLK_SPI0;
break;
case SOCLE_SCU_PCLK_UART2 :
tmp = tmp | SCU_MCLK_UART2;
break;
case SOCLE_SCU_PCLK_UART1 :
tmp = tmp | SCU_MCLK_UART1;
break;
case SOCLE_SCU_PCLK_UART0 :
tmp = tmp | SCU_MCLK_UART0;
break;
default :
SCUMSG("unknow IP number\n");
return -1;
break;
}
}else{
switch(pclk){
case SOCLE_SCU_PCLK_GPIO3 :
tmp = tmp & ~SCU_MCLK_GPIO3;
break;
case SOCLE_SCU_PCLK_GPIO2 :
tmp = tmp & ~SCU_MCLK_GPIO2;
break;
case SOCLE_SCU_PCLK_GPIO1 :
tmp = tmp & ~SCU_MCLK_GPIO1;
break;
case SOCLE_SCU_PCLK_GPIO0 :
tmp = tmp & ~SCU_MCLK_GPIO0;
break;
case SOCLE_SCU_PCLK_ADC :
tmp = tmp & ~SCU_MCLK_ADC;
break;
case SOCLE_SCU_PCLK_PWM :
tmp = tmp & ~SCU_MCLK_PWM;
break;
case SOCLE_SCU_PCLK_WDT :
tmp = tmp & ~SCU_MCLK_WDT;
break;
case SOCLE_SCU_PCLK_RTC :
tmp = tmp & ~SCU_MCLK_RTC;
break;
case SOCLE_SCU_PCLK_TIMER :
tmp = tmp & ~SCU_MCLK_TIMER;
break;
case SOCLE_SCU_PCLK_SDMMC :
tmp = tmp & ~SCU_MCLK_SDMMC;
break;
case SOCLE_SCU_PCLK_I2S :
tmp = tmp & ~SCU_MCLK_I2S;
break;
case SOCLE_SCU_PCLK_I2C :
tmp = tmp & ~SCU_MCLK_I2C;
break;
case SOCLE_SCU_PCLK_SPI1 :
tmp = tmp & ~SCU_MCLK_SPI1;
break;
case SOCLE_SCU_PCLK_SPI0 :
tmp = tmp & ~SCU_MCLK_SPI0;
break;
case SOCLE_SCU_PCLK_UART2 :
tmp = tmp & ~SCU_MCLK_UART2;
break;
case SOCLE_SCU_PCLK_UART1 :
tmp = tmp & ~SCU_MCLK_UART1;
break;
case SOCLE_SCU_PCLK_UART0 :
tmp = tmp & ~SCU_MCLK_UART0;
break;
default :
SCUMSG("unknow IP number\n");
return -1;
break;
}
}
socle_scu_write(tmp, SOCLE_SCU_MCLKEN);
return 0;
}
/* MPLL configuration */
extern int
socle_scu_mpll_clock_set (int mpll_clock)
{
u32 tmp, mpll;
switch(mpll_clock){
case SOCLE_SCU_CPU_CLOCK_33 :
tmp = SCU_CPU_CLOCK_33;
break;
case SOCLE_SCU_CPU_CLOCK_66 :
tmp = SCU_CPU_CLOCK_66;
break;
case SOCLE_SCU_CPU_CLOCK_80 :
tmp = SCU_CPU_CLOCK_80;
break;
case SOCLE_SCU_CPU_CLOCK_100 :
tmp = SCU_CPU_CLOCK_100;
break;
case SOCLE_SCU_CPU_CLOCK_132 :
tmp = SCU_CPU_CLOCK_132;
break;
case SOCLE_SCU_CPU_CLOCK_133 :
tmp = SCU_CPU_CLOCK_133;
break;
case SOCLE_SCU_CPU_CLOCK_150 :
tmp = SCU_CPU_CLOCK_150;
break;
case SOCLE_SCU_CPU_CLOCK_166 :
tmp = SCU_CPU_CLOCK_166;
break;
case SOCLE_SCU_CPU_CLOCK_200 :
tmp = SCU_CPU_CLOCK_200;
break;
case SOCLE_SCU_CPU_CLOCK_240 :
tmp = SCU_CPU_CLOCK_240;
break;
#if 0
case SOCLE_SCU_CPU_CLOCK_258 :
tmp = SCU_CPU_CLOCK_258;
break;
#else
case SOCLE_SCU_CPU_CLOCK_252 :
tmp = SCU_CPU_CLOCK_252;
break;
#endif
case SOCLE_SCU_CPU_CLOCK_264 :
tmp = SCU_CPU_CLOCK_264;
break;
case SOCLE_SCU_CPU_CLOCK_266 :
tmp = SCU_CPU_CLOCK_266;
break;
case SOCLE_SCU_CPU_CLOCK_280 :
tmp = SCU_CPU_CLOCK_280;
break;
case SOCLE_SCU_CPU_CLOCK_300 :
tmp = SCU_CPU_CLOCK_300;
break;
case SOCLE_SCU_CPU_CLOCK_320 :
tmp = SCU_CPU_CLOCK_320;
break;
case SOCLE_SCU_CPU_CLOCK_340 :
tmp = SCU_CPU_CLOCK_340;
break;
case SOCLE_SCU_CPU_CLOCK_350 :
tmp = SCU_CPU_CLOCK_350;
break;
case SOCLE_SCU_CPU_CLOCK_360 :
tmp = SCU_CPU_CLOCK_360;
break;
case SOCLE_SCU_CPU_CLOCK_380 :
tmp = SCU_CPU_CLOCK_380;
break;
case SOCLE_SCU_CPU_CLOCK_390 :
tmp = SCU_CPU_CLOCK_390;
break;
case SOCLE_SCU_CPU_CLOCK_400 :
tmp = SCU_CPU_CLOCK_400;
break;
case SOCLE_SCU_CPU_CLOCK_410 :
tmp = SCU_CPU_CLOCK_410;
break;
case SOCLE_SCU_CPU_CLOCK_420 :
tmp = SCU_CPU_CLOCK_420;
break;
case SOCLE_SCU_CPU_CLOCK_430 :
tmp = SCU_CPU_CLOCK_430;
break;
case SOCLE_SCU_CPU_CLOCK_440 :
tmp = SCU_CPU_CLOCK_440;
break;
case SOCLE_SCU_CPU_CLOCK_450 :
tmp = SCU_CPU_CLOCK_450;
break;
case SOCLE_SCU_CPU_CLOCK_460 :
tmp = SCU_CPU_CLOCK_460;
break;
case SOCLE_SCU_CPU_CLOCK_470 :
tmp = SCU_CPU_CLOCK_470;
break;
case SOCLE_SCU_CPU_CLOCK_480 :
tmp = SCU_CPU_CLOCK_480;
break;
case SOCLE_SCU_CPU_CLOCK_490 :
tmp = SCU_CPU_CLOCK_490;
break;
case SOCLE_SCU_CPU_CLOCK_500 :
tmp = SCU_CPU_CLOCK_500;
break;
case SOCLE_SCU_CPU_CLOCK_510 :
tmp = SCU_CPU_CLOCK_510;
break;
case SOCLE_SCU_CPU_CLOCK_520 :
tmp = SCU_CPU_CLOCK_520;
break;
case SOCLE_SCU_CPU_CLOCK_533 :
tmp = SCU_CPU_CLOCK_533;
break;
default :
SCUMSG("unknow upll clock !!\n");
return -1;
break;
}
mpll = ((socle_scu_read(SOCLE_SCU_MPLLCON) & ~SCU_MPLLCON_PLL_MASK) | (tmp ));
socle_scu_write(mpll, SOCLE_SCU_MPLLCON);
socle_scu_cpu_clock_get();
return 0;
}
