int blkdev_read( const size_t lba, void *buffer, const size_t len )
{
uint32_t i;
for (i=0; i<len+16; i+=4){
#if __mips >= 32
asm volatile(
" cache %0, %1"
: : "i" (0x11) , "R" (*(uint8_t*)(buffer+i))
: "memory"
);
#elif __mips
asm volatile("lw $0, 0(%0)"::"r"((uint32_t)buffer+i));
#endif
}
soclib_io_set(base(BD), BLOCK_DEVICE_LBA, lba);
soclib_io_set(base(BD), BLOCK_DEVICE_BUFFER, (uint32_t)buffer);
soclib_io_set(base(BD), BLOCK_DEVICE_COUNT, len);
soclib_io_set(base(BD), BLOCK_DEVICE_OP, BLOCK_DEVICE_READ);
int state;
do {
state = soclib_io_get(base(BD), BLOCK_DEVICE_STATUS);
} while (state == BLOCK_DEVICE_BUSY);
return state;
}
static void configure_and_start_dma(unsigned int size,
unsigned int from, unsigned int to) {
printf("Configure DMA controller\n\n");
soclib_io_set(base(IP), DMA_RESET_REG, 0);
// Read configuration
soclib_io_set(base(IP), DMA_INFO_REG, DMA_INFO(DMA_READ, DMA_MEM_CONTIG, 0));
soclib_io_set(base(IP), DMA_MEM_REG, from);
soclib_io_set(base(IP), DMA_PHASE_REG, 0);
soclib_io_set(base(IP), DMA_LENGTH_REG, (size*2)>>2);
soclib_io_set(base(IP), DMA_READ_LOOP_REG,
DMA_LOOP_COUNT_STRIDE(1, 0));
// Write configuration
soclib_io_set(base(IP), DMA_INFO_REG, DMA_INFO(DMA_WRITE, DMA_MEM_CONTIG, 0));
soclib_io_set(base(IP), DMA_MEM_REG, to);
soclib_io_set(base(IP), DMA_PHASE_REG, 0);
soclib_io_set(base(IP), DMA_LENGTH_REG, (size*2)>>2);
soclib_io_set(base(IP), DMA_WRITE_LOOP_REG,
DMA_LOOP_COUNT_STRIDE(1, 0));
soclib_io_set(base(IP), DMA_START_REG, 0 /* unused */);
}
int main(void) {
uint32_t time = 0;
int cpu = procnum();
printf("hello From Nios II processor %d\n", procnum());
printf("start FIR application excecution");
printf("\n");
soclib_io_set(timer_address, TIMER_VALUE, 0);
soclib_io_set(timer_address, TIMER_MODE, TIMER_RUNNING);
fir_n(a, b, c);
// time = soclib_io_get(timer_address, TIMER_VALUE);
// printf("\nInterruption caught on proc ");
// printf("%d", cpu); printf(" at time ");
// printf("%d \n", (int) time);
// printf("\n");
printf("end of FIR testing ");
printf("\n");
int *p=(int*)0x0100A000;
*p = -1;
while (1)
;
/* TRAP; */
return (0);
}
int main(void)
{
const int cpu = procnum();
lock_lock(&lock);
printf("Hello from processor %d\n", procnum());
lock_unlock(&lock);
set_irq_handler(irq_handler);
enable_hw_irq(0);
irq_enable();
soclib_io_set(
base(TIMER),
procnum()*TIMER_SPAN+TIMER_PERIOD,
period[cpu]);
soclib_io_set(
base(TIMER),
procnum()*TIMER_SPAN+TIMER_MODE,
TIMER_RUNNING|TIMER_IRQ_ENABLED);
while (1)
pause();
return 0;
}
int blkdev_write( const size_t lba, const void *buffer, const size_t len )
{
soclib_io_set(base(BD), BLOCK_DEVICE_LBA, lba);
soclib_io_set(base(BD), BLOCK_DEVICE_BUFFER, (uint32_t)buffer);
soclib_io_set(base(BD), BLOCK_DEVICE_COUNT, len);
soclib_io_set(base(BD), BLOCK_DEVICE_OP, BLOCK_DEVICE_WRITE);
int state;
do {
state = soclib_io_get(base(BD), BLOCK_DEVICE_STATUS);
} while (state == BLOCK_DEVICE_BUSY);
return state;
}
int main(void)
{
uint32_t i;
const size_t block_size = blkdev_block_size();
const uint32_t n_sectors = blkdev_size();
const size_t crc_block_mul = block_size / 512;
uint8_t data[BLOCKS*block_size];
uint32_t crc = 0;
printf("Hello, world\n");
for ( i=0; i<n_sectors; i+=BLOCKS ) {
uint32_t x = expected_crc[(i+BLOCKS-1)*crc_block_mul];
blkdev_read(i, data, BLOCKS);
// et_hexdump(data, 512*BLOCKS);
crc = do_crc32(crc, data, block_size*BLOCKS);
printf("CRC of %d first blocks is 0x%x, expected: 0x%x\n", i, crc, x);
assert(crc == x);
}
printf("CRC of %d first blocks is 0x%x\n", n_sectors, crc);
for ( i=0; i<100000; ++i )
asm volatile("nop");
soclib_io_set(
base(SIMHELPER),
SIMHELPER_SC_STOP,
0);
while (1);
return 0;
}
void
mwmr_hw_init( void *coproc, enum SoclibMwmrWay way,
unsigned int no, const mwmr_t *mwmr )
{
soclib_io_set( coproc, MWMR_CONFIG_FIFO_WAY, way );
soclib_io_set( coproc, MWMR_CONFIG_FIFO_NO, no );
soclib_io_set( coproc, MWMR_CONFIG_STATUS_ADDR, (uint32_t)&mwmr->status );
soclib_io_set( coproc, MWMR_CONFIG_WIDTH, mwmr->width );
soclib_io_set( coproc, MWMR_CONFIG_DEPTH, mwmr->gdepth );
soclib_io_set( coproc, MWMR_CONFIG_BUFFER_ADDR, (uint32_t)mwmr->buffer );
soclib_io_set( coproc, MWMR_CONFIG_LOCK_ADDR, (uint32_t)mwmr->lock );
soclib_io_set( coproc, MWMR_CONFIG_RUNNING, 1 );
}
void mwmr_wait_fifo_empty( void *coproc, enum SoclibMwmrWay way, unsigned int no, mwmr_t *fifo )
{
//Wait until the RAM fifo is empty
local_mwmr_status_t status;
mwmr_lock( fifo->lock );
rehash_status( fifo, &status );
while (status.usage > 0) {
mwmr_unlock( fifo->lock );
busy_wait(1000);
mwmr_lock( fifo->lock );
rehash_status( fifo, &status );
}
mwmr_unlock( fifo->lock );
//Wait untill all the data is consumed by the coprocessor
int value;
do {
soclib_io_set( coproc, MWMR_CONFIG_FIFO_WAY, way );
soclib_io_set( coproc, MWMR_CONFIG_FIFO_NO, no );
value = soclib_io_get( coproc, /**MWMR_FIFO_STATUS**/MWMR_FIFO_FILL_STATUS );
} while (value > 0);
}
void exit(int level)
{
#ifdef SIMHELPER_BASE
soclib_io_set(
base(SIMHELPER),
SIMHELPER_END_WITH_RETVAL,
level);
#else
# warning No simhelper, exit will do a trap and an infinite loop
#endif
trap();
while(1);
}
void irq_handler(int irq)
{
uint32_t ti;
int left = atomic_add(&max_interrupts, -1);
ti = soclib_io_get(
base(TIMER),
procnum()*TIMER_SPAN+TIMER_VALUE);
printf("IRQ %d received at cycle %d on cpu %d %d interrupts to go\n\n", irq, ti, procnum(), left);
soclib_io_set(
base(TIMER),
procnum()*TIMER_SPAN+TIMER_RESETIRQ,
0);
if(left==0){
soclib_io_set(
base(TIMER),
procnum()*TIMER_SPAN+TIMER_MODE,
0);
}
}
void irq_handler(int irq)
{
printf("IRQ handle\n\n");
uint32_t ti;
int count = atomic_add(&interrupt_counter, 1);
ti = soclib_io_get(
base(TIMER),
procnum()*TIMER_SPAN+TIMER_VALUE);
printf("IRQ %d received at cycle %d on cpu %d, %d interrupts received\n\n", irq, ti, procnum(), count);
soclib_io_set(
base(TIMER),
procnum()*TIMER_SPAN+TIMER_RESETIRQ,
0);
}
void irq_handler(int irq)
{
const int cpu = procnum();
uint32_t ti;
int left = atomic_add(&max_interrupts, -1);
ti = soclib_io_get(
base(TIMER),
cpu*TIMER_SPAN+TIMER_VALUE);
printf("IRQ %d received at cycle %d on cpu %d %d interrupts to go\n\n", irq, ti, cpu, left);
soclib_io_set(
base(TIMER),
cpu*TIMER_SPAN+TIMER_RESETIRQ,
0);
if ( ! left )
exit(0);
}
void mwmr_config( void *coproc, unsigned int no, const uint32_t val )
{
// assert(no < MWMR_IOREG_MAX);
soclib_io_set( coproc, no, val );
}
static inline void set_ctrl(void * base,
unsigned int addr, unsigned int data) {
soclib_io_set(base, CTRL_ADDR_REG, addr);
soclib_io_set(base, CTRL_DATA_REG, data);
}
void irq_handler()
{
char data = soclib_io_get( base(TTY), procnum()*TTY_SPAN + TTY_READ );
soclib_io_set( base(TTY), procnum()*TTY_SPAN + TTY_WRITE, data);
}
int main(void)
{
const int cpu = procnum();
//unsigned int time;
printf("Hello from processor %d\n", procnum());
set_irq_handler(irq_handler);
// irq_set_pil(0);
// enable_hw_irq(0);
// irq_enable();
// included in enable_hw_irq();
printf("TIMER_BASE:%x\n",base(TIMER));
printf("TIMER_SPAN:%d\n",TIMER_SPAN);
printf("TIMER_RERIOD:%d\n",TIMER_PERIOD);
// time = soclib_io_get(
// base(TIMER),
// procnum()*TIMER_SPAN+TIMER_VALUE);
// printf("timer value:%d\n",time );
soclib_io_set(
base(TIMER),
procnum()*TIMER_SPAN+TIMER_PERIOD,
10000);
// period[cpu]);
soclib_io_set(
base(TIMER),
procnum()*TIMER_SPAN+TIMER_MODE,
TIMER_RUNNING|TIMER_IRQ_ENABLED);
int i=0;
/*
for(;i<100000;i++)
{
for(;j<10000;j++)
;
}
*/
for (i=0;i<20;i++)
{
if(i%NCPU==cpu)
{
printf("Fifo %d : %d\n",i,fibo(i));
}
}
time = soclib_io_get(
base(TIMER),
procnum()*TIMER_SPAN+TIMER_VALUE);
finish_bit[cpu]=1;
while(1)
{
int flag=0;
// printf("==========\n");
for(i=0;i<NCPU;i++)
{
flag+=finish_bit[cpu];
// printf("%d ",finish_bit[cpu]);
}
// printf("\n");
if (flag == NCPU)
{
break;
}
}
printf("RUN_TIME:%d\n",time );
while (1)
;
// pause();
return 0;
}
