static int jz_spdif_set_rate(struct device *aic ,struct jz_aic* jz_aic, unsigned long sample_rate){ unsigned long sysclk; struct clk* cgu_aic_clk = jz_aic->clk; __i2s_stop_bitclk(aic); #ifndef CONFIG_PRODUCT_X1000_FPGA sysclk = calculate_cgu_aic_rate(clk_get_rate(cgu_aic_clk->parent), &sample_rate); clk_set_rate(cgu_aic_clk, (sysclk*2)); jz_aic->sysclk = clk_get_rate(cgu_aic_clk); if (jz_aic->sysclk > (sysclk*2)) { printk("external codec set sysclk fail aic = %ld want is %ld .\n",jz_aic->sysclk,sysclk); return -1; } spdif_set_clk(jz_aic, jz_aic->sysclk/2, sample_rate); #else audio_write((253<<13)|(4482),I2SCDR_PRE); *(volatile unsigned int*)0xb0000070 = *(volatile unsigned int*)0xb0000070; audio_write((253<<13)|(4482)|(1<<29),I2SCDR_PRE); audio_write(0,I2SDIV_PRE); #endif __i2s_start_bitclk(aic); spdif_select_ori_sample_freq(aic,sample_rate); spdif_select_sample_freq(aic,sample_rate); return sample_rate; }
static int jz_spdif_set_rate(struct device *aic ,struct jz_aic* jz_aic, unsigned long sample_rate){ struct clk* cgu_aic_clk = jz_aic->clk; __i2s_stop_bitclk(aic); clk_set_rate(cgu_aic_clk, sample_rate); writel(0xa,I2S_CPM_VALID); __i2s_start_bitclk(aic); spdif_select_ori_sample_freq(aic,sample_rate); spdif_select_sample_freq(aic,sample_rate); return sample_rate; }