/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if LPC13xx_SPI_USE_SSP0
spiObjectInit(&SPID1);
SPID1.ssp = LPC_SSP0;
LPC_IOCON->SCK_LOC = LPC13xx_SPI_SCK0_SELECTOR;
#if LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_10
LPC_IOCON->SWCLK_PIO0_10 = 0xC2; /* SCK0 without resistors. */
#elif LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO2_11
LPC_IOCON->PIO2_11 = 0xC1; /* SCK0 without resistors. */
#else /* LPC13xx_SPI_SCK0_SELECTOR == SCK0_IS_PIO0_6 */
LPC_IOCON->PIO0_6 = 0xC2; /* SCK0 without resistors. */
#endif
LPC_IOCON->PIO0_8 = 0xC1; /* MISO0 without resistors. */
LPC_IOCON->PIO0_9 = 0xC1; /* MOSI0 without resistors. */
#endif /* LPC13xx_SPI_USE_SSP0 */
#if LPC13xx_SPI_USE_SSP1
spiObjectInit(&SPID2);
SPID2.ssp = LPC_SSP1;
LPC_IOCON->PIO2_1 = 0xC2; /* SCK1 without resistors. */
LPC_IOCON->PIO2_2 = 0xC2; /* MISO1 without resistors. */
LPC_IOCON->PIO2_3 = 0xC2; /* MOSI1 without resistors. */
#endif /* LPC13xx_SPI_USE_SSP0 */
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if SPC5_SPI_USE_DSPI0
/* Driver initialization.*/
spiObjectInit(&SPID1);
SPID1.dspi = &SPC5_DSPI0;
SPID1.tx_channel = EDMA_ERROR;
SPID1.rx_channel = EDMA_ERROR;
#endif /* SPC5_SPI_USE_DSPI0 */
#if SPC5_SPI_USE_DSPI1
/* Driver initialization.*/
spiObjectInit(&SPID2);
SPID2.dspi = &SPC5_DSPI1;
SPID2.tx_channel = EDMA_ERROR;
SPID2.rx_channel = EDMA_ERROR;
#endif /* SPC5_SPI_USE_DSPI1 */
#if SPC5_SPI_USE_DSPI2
/* Driver initialization.*/
spiObjectInit(&SPID3);
SPID3.dspi = &SPC5_DSPI2;
SPID3.tx_channel = EDMA_ERROR;
SPID3.rx_channel = EDMA_ERROR;
#endif /* SPC5_SPI_USE_DSPI2 */
#if SPC5_SPI_USE_DSPI03
/* Driver initialization.*/
spiObjectInit(&SPID4);
SPID4.dspi = &SPC5_DSPI3;
SPID4.tx_channel = EDMA_ERROR;
SPID4.rx_channel = EDMA_ERROR;
#endif /* SPC5_SPI_USE_DSPI3 */
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if AT91SAM7_SPI_USE_SPI0
spiObjectInit(&SPID1);
SPID1.spi = AT91C_BASE_SPI0;
spi_init(AT91C_BASE_SPI0);
AT91C_BASE_PIOA->PIO_PDR = SPI0_MISO | SPI0_MOSI | SPI0_SCK;
AT91C_BASE_PIOA->PIO_ASR = SPI0_MISO | SPI0_MOSI | SPI0_SCK;
AT91C_BASE_PIOA->PIO_PPUDR = SPI0_MISO | SPI0_MOSI | SPI0_SCK;
AIC_ConfigureIT(AT91C_ID_SPI0,
AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_SPI0_PRIORITY,
SPI0IrqHandler);
#endif
#if AT91SAM7_SPI_USE_SPI1
spiObjectInit(&SPID2);
SPID2.spi = AT91C_BASE_SPI1;
spi_init(AT91C_BASE_SPI1);
AT91C_BASE_PIOA->PIO_PDR = SPI1_MISO | SPI1_MOSI | SPI1_SCK;
AT91C_BASE_PIOA->PIO_BSR = SPI1_MISO | SPI1_MOSI | SPI1_SCK;
AT91C_BASE_PIOA->PIO_PPUDR = SPI1_MISO | SPI1_MOSI | SPI1_SCK;
AIC_ConfigureIT(AT91C_ID_SPI1,
AT91C_AIC_SRCTYPE_HIGH_LEVEL | AT91SAM7_SPI1_PRIORITY,
SPI1IrqHandler);
#endif
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
dummytx = 0xFFFF;
#if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI2
spiObjectInit(&SPID2);
SPID2.spi = SPI2;
SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI3
spiObjectInit(&SPID3);
SPID3.spi = SPI3;
SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if LPC_SPI_USE_SSP0
spiObjectInit(&SPID1);
SPID1.ssp = LPC_SSP0;
#endif /* LPC_SPI_USE_SSP0 */
#if LPC_SPI_USE_SSP1
spiObjectInit(&SPID2);
SPID2.ssp = LPC_SSP1;
#endif /* LPC_SPI_USE_SSP0 */
}
/**
* @brief Low level I2S driver initialization.
*
* @notapi
*/
void i2s_lld_init(void) {
#if STM32_I2S_USE_I2S2
spiObjectInit(&I2SD2);
I2SD2.spi = SPI2;
#endif
#if STM32_I2S_USE_I2S3
spiObjectInit(&I2SD3);
I2SD3.spi = SPI3;
#endif
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if AVR_SPI_USE_SPI1
/* Driver initialization.*/
spiObjectInit(&SPID1);
#endif /* AVR_SPI_USE_SPI1 */
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if PLATFORM_SPI_USE_SPI1 == TRUE
/* Driver initialization.*/
spiObjectInit(&SPID1);
#endif
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if LPC214x_SPI_USE_SSP
spiObjectInit(&SPID1);
SPID1.spd_ssp = SSPBase;
SetVICVector(SPI1IrqHandler, LPC214x_SPI_SSP_IRQ_PRIORITY, SOURCE_SPI1);
#endif
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if LPC122x_SPI_USE_SSP0
spiObjectInit(&SPID1);
SPID1.ssp = LPC_SSP;
LPC_IOCON->PIO0_14 = 0x82; /* SCK0 without resistors. */
LPC_IOCON->PIO0_16 = 0x82; /* MISO0 without resistors. */
LPC_IOCON->PIO0_17 = 0x82; /* MOSI0 without resistors. */
#endif /* LPC122x_SPI_USE_SSP0 */
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void)
{
#if USE_AVR_SPI1 || defined(__DOXYGEN__)
spiObjectInit(&SPID1);
#endif
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void)
{
dummytx = 0xFFFF;
#if TIVA_SPI_USE_SSI0
spiObjectInit(&SPID1);
SPID1.ssi = SSI0;
SPID1.dmarxnr = TIVA_SPI_SSI0_RX_UDMA_CHANNEL;
SPID1.dmatxnr = TIVA_SPI_SSI0_TX_UDMA_CHANNEL;
SPID1.rxchnmap = TIVA_SPI_SSI0_RX_UDMA_MAPPING;
SPID1.txchnmap = TIVA_SPI_SSI0_TX_UDMA_MAPPING;
#endif
#if TIVA_SPI_USE_SSI1
spiObjectInit(&SPID2);
SPID2.ssi = SSI1;
SPID2.dmarxnr = TIVA_SPI_SSI1_RX_UDMA_CHANNEL;
SPID2.dmatxnr = TIVA_SPI_SSI1_TX_UDMA_CHANNEL;
SPID2.rxchnmap = TIVA_SPI_SSI1_RX_UDMA_MAPPING;
SPID2.txchnmap = TIVA_SPI_SSI1_TX_UDMA_MAPPING;
#endif
#if TIVA_SPI_USE_SSI2
spiObjectInit(&SPID3);
SPID3.ssi = SSI2;
SPID3.dmarxnr = TIVA_SPI_SSI2_RX_UDMA_CHANNEL;
SPID3.dmatxnr = TIVA_SPI_SSI2_TX_UDMA_CHANNEL;
SPID3.rxchnmap = TIVA_SPI_SSI2_RX_UDMA_MAPPING;
SPID3.txchnmap = TIVA_SPI_SSI2_TX_UDMA_MAPPING;
#endif
#if TIVA_SPI_USE_SSI3
spiObjectInit(&SPID4);
SPID4.ssi = SSI3;
SPID4.dmarxnr = TIVA_SPI_SSI3_RX_UDMA_CHANNEL;
SPID4.dmatxnr = TIVA_SPI_SSI3_TX_UDMA_CHANNEL;
SPID4.rxchnmap = TIVA_SPI_SSI3_RX_UDMA_MAPPING;
SPID4.txchnmap = TIVA_SPI_SSI3_TX_UDMA_MAPPING;
#endif
}
static void initCC3000SpiHw(void)
{
/* Setup CC3000 SPI pins Chip Select*/
palSetPad(CHIBIOS_CC3000_NSS_PORT, CHIBIOS_CC3000_NSS_PAD);
palSetPadMode(CHIBIOS_CC3000_NSS_PORT, CHIBIOS_CC3000_NSS_PAD,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_LOWEST); /* 400 kHz */
/* General SPI pin setting */
palSetPadMode(CHIBIOS_CC3000_SPI_PORT, CHIBIOS_CC3000_SCK_PAD,
PAL_MODE_ALTERNATE(5) | /* SPI SCK */
PAL_STM32_OTYPE_PUSHPULL |
PAL_STM32_OSPEED_MID2); /* 10 MHz */
palSetPadMode(CHIBIOS_CC3000_SPI_PORT, CHIBIOS_CC3000_MISO_PAD,
PAL_MODE_ALTERNATE(5)); /* SPI MISO */
palSetPadMode(CHIBIOS_CC3000_SPI_PORT, CHIBIOS_CC3000_MOSI_PAD,
PAL_MODE_ALTERNATE(5) | /* SPI MOSI */
PAL_STM32_OTYPE_PUSHPULL |
PAL_STM32_OSPEED_MID2); /* 10 MHz */
/* Setup IRQ pin */
palSetPadMode(CHIBIOS_CC3000_IRQ_PORT, CHIBIOS_CC3000_IRQ_PAD,
PAL_MODE_INPUT_PULLUP);
/* Setup WLAN EN pin.
* With the pin low, we sleep here to make sure
* CC3000 is off.
**/
palClearPad(CHIBIOS_CC3000_WLAN_EN_PORT, CHIBIOS_CC3000_WLAN_EN_PAD);
palSetPadMode(CHIBIOS_CC3000_WLAN_EN_PORT, CHIBIOS_CC3000_WLAN_EN_PAD,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_LOWEST); /* 400 kHz */
/* Initialize EXT and SPI drivers */
extObjectInit(&EXTD1);
spiObjectInit(&SPID1);
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if SAM3XA_SPI_USE_SPI1
/* Driver initialization.*/
spiObjectInit(&SPID1);
#endif
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if SAMA_SPI_USE_SPI0
/* Driver initialization.*/
spiObjectInit(&SPID0);
SPID0.spi = SPI0;
SPID0.dmarx = NULL;
SPID0.dmatx = NULL;
SPID0.rxdmamode = XDMAC_CC_TYPE_PER_TRAN |
XDMAC_CC_MBSIZE_SINGLE |
XDMAC_CC_DSYNC_PER2MEM |
XDMAC_CC_PROT_SEC |
XDMAC_CC_CSIZE_CHK_1 |
XDMAC_CC_DWIDTH_BYTE |
XDMAC_CC_SIF_AHB_IF1 |
XDMAC_CC_DIF_AHB_IF0 |
XDMAC_CC_SAM_FIXED_AM |
XDMAC_CC_DAM_INCREMENTED_AM |
XDMAC_CC_PERID(PERID_SPI0_RX);
SPID0.txdmamode = XDMAC_CC_TYPE_PER_TRAN |
XDMAC_CC_MBSIZE_SINGLE |
XDMAC_CC_DSYNC_MEM2PER |
XDMAC_CC_PROT_SEC |
XDMAC_CC_CSIZE_CHK_1 |
XDMAC_CC_DWIDTH_BYTE |
XDMAC_CC_SIF_AHB_IF0 |
XDMAC_CC_DIF_AHB_IF1 |
XDMAC_CC_SAM_INCREMENTED_AM |
XDMAC_CC_DAM_FIXED_AM |
XDMAC_CC_PERID(PERID_SPI0_TX);
#endif /* SAMA_SPI_USE_SPI0 */
#if SAMA_SPI_USE_SPI1
/* Driver initialization.*/
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
SPID1.dmarx = NULL;
SPID1.dmatx = NULL;
SPID1.rxdmamode = XDMAC_CC_TYPE_PER_TRAN |
XDMAC_CC_MBSIZE_SINGLE |
XDMAC_CC_DSYNC_PER2MEM |
XDMAC_CC_PROT_SEC |
XDMAC_CC_CSIZE_CHK_1 |
XDMAC_CC_DWIDTH_BYTE |
XDMAC_CC_SIF_AHB_IF1 |
XDMAC_CC_DIF_AHB_IF0 |
XDMAC_CC_SAM_FIXED_AM |
XDMAC_CC_DAM_INCREMENTED_AM |
XDMAC_CC_PERID(PERID_SPI1_RX);
SPID1.txdmamode = XDMAC_CC_TYPE_PER_TRAN |
XDMAC_CC_MBSIZE_SINGLE |
XDMAC_CC_DSYNC_MEM2PER |
XDMAC_CC_PROT_SEC |
XDMAC_CC_CSIZE_CHK_1 |
XDMAC_CC_DWIDTH_BYTE |
XDMAC_CC_SIF_AHB_IF0 |
XDMAC_CC_DIF_AHB_IF1 |
XDMAC_CC_SAM_INCREMENTED_AM |
XDMAC_CC_DAM_FIXED_AM |
XDMAC_CC_PERID(PERID_SPI1_TX);
#endif /* SAMA_SPI_USE_SPI1 */
}
static void initialiseCC3000(void)
{
#ifdef STM32L1XX_MD
/* SPI Config */
cc3000SpiConfig.end_cb = NULL;
cc3000SpiConfig.ssport = CHIBIOS_CC3000_NSS_PORT;
cc3000SpiConfig.sspad = CHIBIOS_CC3000_NSS_PAD;
#if 1
cc3000SpiConfig.cr1 = SPI_CR1_CPHA | /* 2nd clock transition first data capture edge */
(SPI_CR1_BR_1 | SPI_CR1_BR_0 ); /* BR: 011 - 2 MHz */
/* Setup SPI pins */
palSetPad(CHIBIOS_CC3000_NSS_PORT, CHIBIOS_CC3000_NSS_PAD);
palSetPadMode(CHIBIOS_CC3000_NSS_PORT, CHIBIOS_CC3000_NSS_PAD,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_LOWEST); /* 400 kHz */
palSetPadMode(CHIBIOS_CC3000_SPI_PORT, CHIBIOS_CC3000_SCK_PAD,
PAL_MODE_ALTERNATE(5) | /* SPI */
PAL_STM32_OTYPE_PUSHPULL |
PAL_STM32_OSPEED_MID2); /* 10 MHz */
palSetPadMode(CHIBIOS_CC3000_SPI_PORT, CHIBIOS_CC3000_MISO_PAD,
PAL_MODE_ALTERNATE(5)); /* SPI */
palSetPadMode(CHIBIOS_CC3000_SPI_PORT, CHIBIOS_CC3000_MOSI_PAD,
PAL_MODE_ALTERNATE(5) | /* SPI */
PAL_STM32_OTYPE_PUSHPULL |
PAL_STM32_OSPEED_MID2); /* 10 MHz */
#else
#if 0
cc3000SpiConfig.cr1 = SPI_CR1_CPHA | /* 2nd clock transition first data capture edge */
(SPI_CR1_BR_0); /* BR: 001 - 8 MHz */
#endif
cc3000SpiConfig.cr1 = SPI_CR1_CPHA | /* 2nd clock transition first data capture edge */
(SPI_CR1_BR_1 | SPI_CR1_BR_0 ); /* BR: 011 - 2 MHz */
/* Setup SPI pins */
palSetPad(CHIBIOS_CC3000_PORT, CHIBIOS_CC3000_NSS_PAD);
palSetPadMode(CHIBIOS_CC3000_PORT, CHIBIOS_CC3000_NSS_PAD,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(CHIBIOS_CC3000_PORT, CHIBIOS_CC3000_SCK_PAD,
PAL_MODE_ALTERNATE(5) | /* SPI */
PAL_STM32_OTYPE_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST);
palSetPadMode(CHIBIOS_CC3000_PORT, CHIBIOS_CC3000_MISO_PAD,
PAL_MODE_ALTERNATE(5));
palSetPadMode(CHIBIOS_CC3000_PORT, CHIBIOS_CC3000_MOSI_PAD,
PAL_MODE_ALTERNATE(5) | /* SPI */
PAL_STM32_OTYPE_PUSHPULL |
PAL_STM32_OSPEED_MID2);
#endif
/* Setup IRQ pin */
palSetPadMode(CHIBIOS_CC3000_IRQ_PORT, CHIBIOS_CC3000_IRQ_PAD,
PAL_MODE_INPUT);
/* Setup WLAN EN pin.
With the pin low, we sleep here to make sure CC3000 is off. */
palClearPad(CHIBIOS_CC3000_WLAN_EN_PORT, CHIBIOS_CC3000_WLAN_EN_PAD);
palSetPadMode(CHIBIOS_CC3000_WLAN_EN_PORT, CHIBIOS_CC3000_WLAN_EN_PAD,
PAL_MODE_OUTPUT_PUSHPULL |
PAL_STM32_OSPEED_LOWEST); /* 400 kHz */
#endif /* STM32L1XX_MD */
chMtxInit(&cc3000ApiMutex);
extObjectInit(&CC3000_EXT_DRIVER);
spiObjectInit(&CC3000_SPI_DRIVER);
chThdSleep(MS2ST(500));
cc3000ChibiosWlanInit(&CC3000_SPI_DRIVER, &cc3000SpiConfig,
&CC3000_EXT_DRIVER, &cc3000ExtConfig,
0,0,0, debugPrint);
}
/**
* @brief Low level SPI driver initialization.
*
* @notapi
*/
void spi_lld_init(void) {
#if STM32_SPI_USE_SPI1
spiObjectInit(&SPID1);
SPID1.spi = SPI1;
SPID1.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);
SPID1.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);
SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI2
spiObjectInit(&SPID2);
SPID2.spi = SPI2;
SPID2.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);
SPID2.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);
SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI3
spiObjectInit(&SPID3);
SPID3.spi = SPI3;
SPID3.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);
SPID3.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);
SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI4
spiObjectInit(&SPID4);
SPID4.spi = SPI4;
SPID4.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM);
SPID4.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM);
SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI5
spiObjectInit(&SPID5);
SPID5.spi = SPI5;
SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM);
SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM);
SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
#if STM32_SPI_USE_SPI6
spiObjectInit(&SPID6);
SPID6.spi = SPI6;
SPID6.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM);
SPID6.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM);
SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_P2M |
STM32_DMA_CR_TCIE |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |
STM32_DMA_CR_DIR_M2P |
STM32_DMA_CR_DMEIE |
STM32_DMA_CR_TEIE;
#endif
}
