FPGA_STATUS fpga_spi_loopback(uint8_t* data,uint32_t data_len)
{
FPGA_STATUS ret;
uint8_t i,rcvd[100];
uint8_t writecmd = CMDPKT_FPGA_WRITE,readcmd=CMDPKT_FPGA_READ;
//initialise SPI
ret = fpga_spiclaim(SPI_FPGA_OPFREQ);
if (ret) {
spi_release();
return FAIL;
}
//transmit data
spi_xfer(1,&writecmd,NULL,0);
spi_xfer(data_len,data,NULL,0);
spi_release();
delay (100);
platform_write("DATA sent successfully \n");
//receive the data
ret = fpga_spiclaim(SPI_FPGA_OPFREQ);
if (ret) {
spi_release();
return FAIL;
}
spi_cmd_read(&readcmd,1,rcvd,data_len);
//verify the data
for(i=0;i<data_len;i++)
{
if(rcvd[i]=!data[i])
platform_write("error occurred for byte %d expected :%d received %d",i,data[i],rcvd[i]);
else
platform_write("DATA verification successful \n");
}
spi_release();
return SUCCESS;
}
/* PWC(ext) access functions */
int pwc_reg_read_ext(unsigned char addr, unsigned char *data)
{
int ret = 0;
if (data == NULL)
return -EINVAL;
if (pwc_ext_rw_table[addr] & PWC_REG_READONLY) {
ret = spi_cmd_read(&device_ext_config_read, &addr, data, 0);
if (ret < 0) {
printk(KERN_INFO
"pwc_reg_read(): spi_read error(addr=0x%02x)\n",
addr >> 1);
return ret;
}
