void programcmd(unsigned char seqnum)
{
unsigned char tmp,tmp2,addressing_is_word,ci,cj,cstatus;
unsigned int answerlen;
unsigned long poll_address=0;
unsigned int i,nbytes;
// distingush addressing CMD_READ_EEPROM_ISP (8bit) and CMD_READ_FLASH_ISP (16bit)
addressing_is_word=1; // 16 bit is default
switch(msg_buf[0]){
case CMD_SIGN_ON:
// prepare answer:
msg_buf[0] = CMD_SIGN_ON; // 0x01
msg_buf[1] = STATUS_CMD_OK; // 0x00
msg_buf[2] = 8; //len
strcpy((char *)&(msg_buf[3]),"AVRISP_2"); // note: this copied also the null termination
answerlen=11;
break;
case CMD_SET_PARAMETER:
// not implemented:
// PARAM_VTARGET
// PARAM_VADJUST
// PARAM_OSC_PSCALE
// PARAM_OSC_CMATCH
if (msg_buf[1]==PARAM_SCK_DURATION){
spi_set_sck_duration(msg_buf[2]);
}else if(msg_buf[1]==PARAM_RESET_POLARITY){
param_reset_polarity=msg_buf[2];
}else if(msg_buf[1]==PARAM_CONTROLLER_INIT){
param_controller_init=msg_buf[2];
}
answerlen = 2;
//msg_buf[0] = CMD_SET_PARAMETER;
msg_buf[1] = STATUS_CMD_OK;
break;
case CMD_GET_PARAMETER:
tmp=0xff;
switch(msg_buf[1])
{
case PARAM_BUILD_NUMBER_LOW:
tmp = CONFIG_PARAM_BUILD_NUMBER_LOW;
break;
case PARAM_BUILD_NUMBER_HIGH:
tmp = CONFIG_PARAM_BUILD_NUMBER_HIGH;
break;
case PARAM_HW_VER:
tmp = CONFIG_PARAM_HW_VER;
break;
case PARAM_SW_MAJOR:
tmp = CONFIG_PARAM_SW_MAJOR;
break;
case PARAM_SW_MINOR:
tmp = CONFIG_PARAM_SW_MINOR;
break;
case PARAM_VTARGET:
tmp = CONFIG_PARAM_VTARGET;
break;
case PARAM_VADJUST:
tmp = CONFIG_PARAM_VADJUST;
break;
case PARAM_SCK_DURATION:
tmp = spi_get_sck_duration();
break;
case PARAM_RESET_POLARITY: // is actually write only, list anyhow
tmp = param_reset_polarity;
break;
case PARAM_CONTROLLER_INIT:
tmp = param_controller_init;
break;
case PARAM_OSC_PSCALE:
tmp = CONFIG_PARAM_OSC_PSCALE;
break;
case PARAM_OSC_CMATCH:
tmp = CONFIG_PARAM_OSC_CMATCH;
break;
case PARAM_TOPCARD_DETECT: // stk500 only
tmp = 0; // no card ??
break;
case PARAM_DATA: // stk500 only
tmp = 0;
break;
default:
break;
}
if (tmp ==0xff){
// command not understood
answerlen = 2;
//msg_buf[0] = CMD_GET_PARAMETER;
msg_buf[1] = STATUS_CMD_UNKNOWN;
}else{
answerlen = 3;
//msg_buf[0] = CMD_GET_PARAMETER;
msg_buf[1] = STATUS_CMD_OK;
msg_buf[2] = tmp;
}
break;
case CMD_LOAD_ADDRESS:
address = ((unsigned long)msg_buf[1])<<24;
address |= ((unsigned long)msg_buf[2])<<16;
address |= ((unsigned long)msg_buf[3])<<8;
address |= ((unsigned long)msg_buf[4]);
answerlen = 2;
//msg_buf[0] = CMD_LOAD_ADDRESS;
msg_buf[1] = STATUS_CMD_OK;
break;
case CMD_FIRMWARE_UPGRADE:
// firmare upgrade is not supported this way
answerlen = 2;
//msg_buf[0] = CMD_FIRMWARE_UPGRADE;
msg_buf[1] = STATUS_CMD_FAILED;
break;
case CMD_ENTER_PROGMODE_ISP:
// The syntax of this command is as follows:
// 0: Command ID 1 byte, CMD_ENTER_ PROGMODE_ISP
// 1: timeout 1 byte, Command time-out (in ms)
// 2: stabDelay 1 byte, Delay (in ms) used for pin stabilization
// 3: cmdexeDelay 1 byte, Delay (in ms) in connection with the EnterProgMode command execution
// 4: synchLoops 1 byte, Number of synchronization loops
// 5: byteDelay 1 byte, Delay (in ms) between each byte in the EnterProgMode command.
// 6: pollValue 1 byte, Poll value: 0x53 for AVR, 0x69 for AT89xx
// 7: pollIndex 1 byte, Start address, received byte: 0 = no polling, 3 = AVR, 4 = AT89xx
// cmd1 1 byte
// cmd2 1 byte
// cmd3 1 byte
// cmd4 1 byte
LED_ON;
spi_init();
delay_ms(msg_buf[2]); // stabDelay
answerlen=2;
//msg_buf[0] = CMD_ENTER_PROGMODE_ISP;
// set default to failed:
msg_buf[1] = STATUS_CMD_FAILED;
//connect to the target
i=0;
// limit the loops:
if (msg_buf[4]> 32){
msg_buf[4]=32;
}
if (msg_buf[5] < 3){
// minimum delay
msg_buf[5]=3;
}
while(i<msg_buf[4]){//synchLoops
wd_kick();
LED_ON; // blink during init
i++;
spi_mastertransmit(msg_buf[8]);//cmd1
delay_ms(msg_buf[5]); //byteDelay
spi_mastertransmit(msg_buf[9]); //cmd2
delay_ms(msg_buf[5]); //byteDelay
LED_OFF; // blink during init
tmp=spi_mastertransmit(msg_buf[10]);//cmd3
delay_ms(msg_buf[5]); //byteDelay
tmp2=spi_mastertransmit(msg_buf[11]);//cmd4
delay_ms(msg_buf[5]); //byteDelay
//7=pollIndex, 6=pollValue
if(msg_buf[7]==3 && tmp==msg_buf[6]) {
msg_buf[1] = STATUS_CMD_OK;
}
//7=pollIndex, 6=pollValue
if(msg_buf[7]!=3 && tmp2==msg_buf[6]) {
msg_buf[1] = STATUS_CMD_OK;
}
if(msg_buf[7]==0) { //pollIndex
msg_buf[1] = STATUS_CMD_OK;
}
// causes problems with MULTI spi_clock_pulse();
if(msg_buf[1] == STATUS_CMD_OK)
{
LED_ON;
i=msg_buf[4];// end loop
}
}
break;
case CMD_LEAVE_PROGMODE_ISP:
spi_disable();
LED_OFF;
answerlen = 2;
//msg_buf[0] = CMD_LEAVE_PROGMODE_ISP;
msg_buf[1] = STATUS_CMD_OK;
break;
case CMD_CHIP_ERASE_ISP:
spi_mastertransmit(msg_buf[3]);
spi_mastertransmit(msg_buf[4]);
spi_mastertransmit(msg_buf[5]);
spi_mastertransmit(msg_buf[6]);
if(msg_buf[2]==0) {
// pollMethod use delay
delay_ms(msg_buf[1]); // eraseDelay
} else {
// pollMethod RDY/BSY cmd
ci=150; // timeout
while((spi_mastertransmit_32(0xF0000000)&1)&&ci){
ci--;
}
}
answerlen = 2;
//msg_buf[0] = CMD_CHIP_ERASE_ISP;
msg_buf[1] = STATUS_CMD_OK;
break;
case CMD_PROGRAM_EEPROM_ISP:
addressing_is_word=0; // address each byte
case CMD_PROGRAM_FLASH_ISP:
// msg_buf[0] CMD_PROGRAM_FLASH_ISP = 0x13
// msg_buf[1] NumBytes H
// msg_buf[2] NumBytes L
// msg_buf[3] mode
// msg_buf[4] delay
// msg_buf[5] cmd1 (Load Page, Write Program Memory)
// msg_buf[6] cmd2 (Write Program Memory Page)
// msg_buf[7] cmd3 (Read Program Memory)
// msg_buf[8] poll1 (value to poll)
// msg_buf[9] poll2
// msg_buf[n+10] Data
poll_address=0;
ci=150;
// set a minimum delay
if (msg_buf[4] < 3){
msg_buf[4]=3;
}
// set a max delay
if (msg_buf[4] > 24){
msg_buf[4]=24;
}
saddress=address; // previous address, start address
nbytes = ((unsigned int)msg_buf[1])<<8;
nbytes |= msg_buf[2];
if (nbytes> 280){
// corrupted message
answerlen = 2;
msg_buf[1] = STATUS_CMD_FAILED;
break;
}
wd_kick();
// store the original mode:
tmp2=msg_buf[3];
// result code
cstatus=STATUS_CMD_OK;
// msg_buf[3] test Word/Page Mode bit:
if ((msg_buf[3]&1)==0){
// word mode
for(i=0;i<nbytes;i++)
{
// The Low/High byte selection bit is
// bit number 3. Set high byte for uneven bytes
if(addressing_is_word && i&1) {
// high byte
spi_mastertransmit(msg_buf[5]|(1<<3));
} else {
// low byte
spi_mastertransmit(msg_buf[5]);
}
spi_mastertransmit_16(address&0xFFFF);
spi_mastertransmit(msg_buf[i+10]);
// if the data byte is not same as poll value
// in that case we can do polling:
if(msg_buf[8]!=msg_buf[i+10]) {
poll_address = address&0xFFFF;
// restore the possibly modifed mode:
msg_buf[3]=tmp2;
} else {
//switch the mode to timed delay (waiting), for this word
msg_buf[3]= 0x02;
}
//
wd_kick();
if (!addressing_is_word){
// eeprom writing, eeprom needs more time
delay_ms(1);
}
//check the different polling mode methods
if(msg_buf[3]& 0x04) {
//data value polling
tmp=msg_buf[8];
ci=150; // timeout
while(tmp==msg_buf[8] && ci ){
// The Low/High byte selection bit is
// bit number 3. Set high byte for uneven bytes
// Read data:
if(addressing_is_word && i&1) {
spi_mastertransmit(msg_buf[7]|(1<<3));
} else {
spi_mastertransmit(msg_buf[7]);
}
spi_mastertransmit_16(poll_address);
tmp=spi_mastertransmit(0x00);
ci--;
}
} else if(msg_buf[3]&0x08){
//RDY/BSY polling
ci=150; // timeout
while((spi_mastertransmit_32(0xF0000000)&1)&&ci){
ci--;
}
}else{
//timed delay (waiting)
delay_ms(msg_buf[4]);
}
if (addressing_is_word){
//increment word address only when we have an uneven byte
if(i&1) address++;
}else{
//increment address
address++;
}
if (ci==0){
cstatus=STATUS_CMD_TOUT;
}
}
}else{
//page mode, all modern chips
for(i=0;i<nbytes;i++)
{
wd_kick();
// The Low/High byte selection bit is
// bit number 3. Set high byte for uneven bytes
if(addressing_is_word && i&1) {
spi_mastertransmit(msg_buf[5]|(1<<3));
} else {
spi_mastertransmit(msg_buf[5]);
}
spi_mastertransmit_16(address&0xFFFF);
spi_mastertransmit(msg_buf[i+10]);
// that the data byte is not same as poll value
// in that case we can do polling:
if(msg_buf[8]!=msg_buf[i+10]) {
poll_address = address&0xFFFF;
} else {
//switch the mode to timed delay (waiting)
//we must preserve bit 0x80
msg_buf[3]= (msg_buf[3]&0x80)|0x10;
}
if (addressing_is_word){
//increment word address only when we have an uneven byte
if(i&1) address++;
}else{
address++;
}
}
wd_kick();
//page mode check result:
//
// stk sets the Write page bit (7) if the page is complete
// and we should write it.
if(msg_buf[3]&0x80) {
spi_mastertransmit(msg_buf[6]);
spi_mastertransmit_16(saddress&0xFFFF);
spi_mastertransmit(0);
//
if (!addressing_is_word){
// eeprom writing, eeprom needs more time
delay_ms(1);
}
//check the different polling mode methods
ci=150; // timeout
if(msg_buf[3]&0x20 && poll_address) {
//Data value polling
tmp=msg_buf[8];
while(tmp==msg_buf[8] && ci){
// The Low/High byte selection bit is
// bit number 3. Set high byte for uneven bytes
// Read data:
if(poll_address&1) {
spi_mastertransmit(msg_buf[7]|(1<<3));
} else {
spi_mastertransmit(msg_buf[7]);
}
spi_mastertransmit_16(poll_address);
tmp=spi_mastertransmit(0x00);
ci--;
}
if (ci==0){
cstatus=STATUS_CMD_TOUT;
}
} else if(msg_buf[3]& 0x40){
//RDY/BSY polling
while((spi_mastertransmit_32(0xF0000000)&1)&&ci){
ci--;
}
if (ci==0){
cstatus=STATUS_RDY_BSY_TOUT;
}
}else{
// simple waiting
delay_ms(msg_buf[4]);
}
}
}
answerlen = 2;
//msg_buf[0] = CMD_PROGRAM_FLASH_ISP; or CMD_PROGRAM_EEPROM_ISP
msg_buf[1] = cstatus;
break;
case CMD_READ_EEPROM_ISP:
addressing_is_word=0; // address each byte
case CMD_READ_FLASH_ISP:
// msg_buf[1] and msg_buf[2] NumBytes
// msg_buf[3] cmd
nbytes = ((unsigned int)msg_buf[1])<<8;
nbytes |= msg_buf[2];
tmp = msg_buf[3];
// limit answer len, prevent overflow:
if (nbytes> 280){
nbytes=280;
}
//
for(i=0;i<nbytes;i++)
{
wd_kick();
//Select Low or High-Byte
if(addressing_is_word && i&1) {
spi_mastertransmit(tmp|(1<<3));
} else {
spi_mastertransmit(tmp);
}
spi_mastertransmit_16(address&0xFFFF);
msg_buf[i+2] = spi_mastertransmit(0);
if (addressing_is_word){
//increment word address only when we have an uneven byte
if(i&1) address++;
}else{
address++;
}
}
answerlen = nbytes+3;
//msg_buf[0] = CMD_READ_FLASH_ISP; or CMD_READ_EEPROM_ISP
msg_buf[1] = STATUS_CMD_OK;
msg_buf[nbytes+2] = STATUS_CMD_OK;
break;
case CMD_PROGRAM_LOCK_ISP:
case CMD_PROGRAM_FUSE_ISP:
spi_mastertransmit(msg_buf[1]);
spi_mastertransmit(msg_buf[2]);
spi_mastertransmit(msg_buf[3]);
spi_mastertransmit(msg_buf[4]);
answerlen =3;
// msg_buf[0] = CMD_PROGRAM_FUSE_ISP; or CMD_PROGRAM_LOCK_ISP
msg_buf[1] = STATUS_CMD_OK;
msg_buf[2] = STATUS_CMD_OK;
break;
case CMD_READ_OSCCAL_ISP:
case CMD_READ_SIGNATURE_ISP:
case CMD_READ_LOCK_ISP:
case CMD_READ_FUSE_ISP:
for(ci=0;ci<4;ci++){
tmp = spi_mastertransmit(msg_buf[ci+2]);
if (msg_buf[1] == (ci + 1)){
msg_buf[2] = tmp;
}
delay_ms(5);
}
answerlen = 4;
// msg_buf[0] = CMD_READ_FUSE_ISP; or CMD_READ_LOCK_ISP or ...
msg_buf[1] = STATUS_CMD_OK;
// msg_buf[2] is the data (fuse byte)
msg_buf[3] = STATUS_CMD_OK;
break;
case CMD_SPI_MULTI:
// 0: CMD_SPI_MULTI
// 1: NumTx
// 2: NumRx
// 3: RxStartAddr counting from zero
// 4+: TxData (len in NumTx)
// example: 0x1d 0x04 0x04 0x00 0x30 0x00 0x00 0x00
tmp=msg_buf[2];
tmp2=msg_buf[3];
cj=0;
ci=0;
for (cj=0; cj<msg_buf[1]; cj++) {
if (cj >= tmp2 && ci <tmp){
// store answer starting from msg_buf[2]
msg_buf[ci+2]=spi_mastertransmit(msg_buf[cj+4]);
ci++;
}else{
spi_mastertransmit(msg_buf[cj+4]);
}
delay_ms(5);
}
// padd with zero:
while(ci<tmp){
msg_buf[ci+2]=0;
ci++;
}
answerlen = ci+3;
// msg_buf[0] = CMD_SPI_MULTI
msg_buf[1] = STATUS_CMD_OK;
// msg_buf[2...ci+1] is the data
msg_buf[ci+2] = STATUS_CMD_OK;
break;
default:
// we should not come here
answerlen = 2;
msg_buf[1] = STATUS_CMD_UNKNOWN;
break;
}
transmit_answer(seqnum,answerlen);
}
void board_init(void)
{
ioport_init();
//SPI interface initialization
#ifdef CONF_SPI
//MISO
ioport_set_pin_peripheral_mode(PIN_PA21, IOPORT_MODE_MUX_A);
//MOSI
ioport_set_pin_peripheral_mode(PIN_PA22, IOPORT_MODE_MUX_A);
//SCK
ioport_set_pin_peripheral_mode(PIN_PA23, IOPORT_MODE_MUX_A);
//CS0
ioport_set_pin_peripheral_mode(PIN_PA24, IOPORT_MODE_MUX_A);
//CS1
ioport_set_pin_peripheral_mode(PIN_PA13, IOPORT_MODE_MUX_C);
//CS2
ioport_set_pin_peripheral_mode(PIN_PA14, IOPORT_MODE_MUX_C);
//CS3
ioport_set_pin_peripheral_mode(PIN_PB12, IOPORT_MODE_MUX_B);
spi_enable_clock(SPI);
spi_disable(SPI);
spi_reset(SPI);
spi_set_master_mode(SPI);
spi_disable_mode_fault_detect(SPI);
spi_disable_loopback(SPI);
spi_set_variable_peripheral_select(SPI);
spi_disable_peripheral_select_decode(SPI);
//spi_set_peripheral_chip_select_value(SPI, SPI_CHSEL);
//spi_set_transfer_delay(SPI, 1, 50, 0);
//spi_set_delay_between_chip_select(SPI, 0);
for(char i = 0; i < 4; i++){
spi_set_bits_per_transfer(SPI, i, 8);
//spi_set_baudrate_div(SPI, i, spi_calc_baudrate_div(1000000, sysclk_get_cpu_hz()));
spi_set_baudrate_div(SPI, i, (sysclk_get_cpu_hz() / 500000));
spi_configure_cs_behavior(SPI, i, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(SPI, i, 0);
spi_set_clock_phase(SPI, i, 0);
}
spi_enable(SPI);
#endif
//USART0 initialization
#ifdef CONF_USART0
//USART0 RXD
ioport_set_pin_peripheral_mode(PIN_PA11, IOPORT_MODE_MUX_A);
#if SAM4L
sysclk_enable_peripheral_clock(USART0);
#endif
//USART0 configuration struct
const sam_usart_opt_t usart0_console_settings = {
CONF_USART_0_BAUDRATE,
CONF_USART_0_CHAR_LENGTH,
CONF_USART_0_PARITY,
CONF_USART_0_STOP_BITS,
US_MR_CHMODE_NORMAL
};
usart_init_rs232(USART0, &usart0_console_settings, sysclk_get_main_hz());
usart_enable_tx(USART0);
usart_enable_rx(USART0);
usart_enable_interrupt(USART0, US_IER_RXRDY);
NVIC_SetPriority(USART0_IRQn, 10);
NVIC_EnableIRQ(USART0_IRQn);
#endif
//USART1 initialization
#ifdef CONF_USART1
//USART1 TXD
ioport_set_pin_peripheral_mode(PIN_PA16, IOPORT_MODE_MUX_A);
//USART1 RXD
ioport_set_pin_peripheral_mode(PIN_PA15, IOPORT_MODE_MUX_A);
#if SAM4L
sysclk_enable_peripheral_clock(USART1);
#endif
//USART1 configuration struct
const sam_usart_opt_t usart1_console_settings = {
CONF_USART_1_BAUDRATE,
CONF_USART_1_CHAR_LENGTH,
CONF_USART_1_PARITY,
CONF_USART_1_STOP_BITS,
US_MR_CHMODE_NORMAL
};
usart_init_rs232(USART1, &usart1_console_settings, sysclk_get_main_hz());
usart_enable_tx(USART1);
usart_enable_rx(USART1);
usart_enable_interrupt(USART1, US_IER_RXRDY);
//NVIC_SetPriority(USART0_IRQn, 10);
NVIC_EnableIRQ(USART1_IRQn);
#endif
#ifdef CONF_TWIMS1
//SDA
ioport_set_pin_peripheral_mode(PIN_PB00, IOPORT_MODE_MUX_A);
//SCL
ioport_set_pin_peripheral_mode(PIN_PB01, IOPORT_MODE_MUX_A);
/* Set TWIM options */
uint32_t cpu_speed = 0;
cpu_speed = sysclk_get_peripheral_bus_hz(EXAMPLE_TWIM);
struct twim_config opts = {
.twim_clk = sysclk_get_cpu_hz(), //Importante
.speed = TWIM_MASTER_SPEED,
.hsmode_speed = 0,
.data_setup_cycles = 0,
.hsmode_data_setup_cycles = 0,
.smbus = false,
.clock_slew_limit = 0,
.clock_drive_strength_low = 0,
.data_slew_limit = 0,
.data_drive_strength_low = 0,
.hs_clock_slew_limit = 0,
.hs_clock_drive_strength_high = 0,
.hs_clock_drive_strength_low = 0,
.hs_data_slew_limit = 0,
.hs_data_drive_strength_low = 0,
};
/* Initialize the TWIM Module */
twim_set_callback(EXAMPLE_TWIM, 0, twim_default_callback, 1);
twim_set_config(EXAMPLE_TWIM, &opts);
#endif
//ADS 1294R initialization
#ifdef CONF_ADS
ADS_ioconfig();
Soft_Reset_ADS1298();
delay_us(50);
Stop_Read_Data_Continuous();
/*Configuration register 1*/
ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_1_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x06);
/*Configuration register 2*/
ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_2_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*Configuration register 3*/
ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_3_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0xDC);
/*Channel 1 register*/
ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_1_SET_REGISTER, SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*Channel 2 register*/
ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_2_SET_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*Channel 3 register*/
ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_3_SET_REGISTER , SINGLE_BYTE);
ADS1298_SPI_Data(0x00);
/*RLD_SENSP register*/
ADS1298_SPI_Address_Byte_Count(WRITE_RIGHT_LEG_DRIVE_SENSE_POSITIVE_REGISTER, SINGLE_BYTE);
ADS1298_SPI_Data(0x0F);
/*RLD_SENSN register*/
ADS1298_SPI_Address_Byte_Count(WRITE_RIGHT_LEG_DRIVE_SENSE_NEGATIVE_REGISTER, SINGLE_BYTE);
ADS1298_SPI_Data(0x0F);
/*Respiration control register*/
//Respiration channel not enabled
#endif
}
/**
* \brief KSZ8851SNL initialization function.
*
* \return 0 on success, 1 on communication error.
*/
uint32_t ksz8851snl_init(void)
{
uint32_t count = 10;
uint16_t dev_id = 0;
uint8_t id_ok = 0;
/* Configure the SPI peripheral. */
spi_enable_clock(KSZ8851SNL_SPI);
spi_disable(KSZ8851SNL_SPI);
spi_reset(KSZ8851SNL_SPI);
spi_set_master_mode(KSZ8851SNL_SPI);
spi_disable_mode_fault_detect(KSZ8851SNL_SPI);
spi_set_peripheral_chip_select_value(KSZ8851SNL_SPI, ~(uint32_t)(1UL << KSZ8851SNL_CS_PIN));
spi_set_fixed_peripheral_select(KSZ8851SNL_SPI);
//spi_disable_peripheral_select_decode(KSZ8851SNL_SPI);
spi_set_clock_polarity(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_POLARITY);
spi_set_clock_phase(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_PHASE);
spi_set_bits_per_transfer(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN,
SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, (sysclk_get_cpu_hz() / KSZ8851SNL_CLOCK_SPEED));
// spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, CONFIG_SPI_MASTER_DELAY_BS,
// CONFIG_SPI_MASTER_DELAY_BCT);
spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, 0, 0);
spi_enable(KSZ8851SNL_SPI);
/* Get pointer to UART PDC register base. */
g_p_spi_pdc = spi_get_pdc_base(KSZ8851SNL_SPI);
pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);
/* Control RSTN and CSN pin from the driver. */
gpio_configure_pin(KSZ8851SNL_CSN_GPIO, KSZ8851SNL_CSN_FLAGS);
gpio_set_pin_high(KSZ8851SNL_CSN_GPIO);
gpio_configure_pin(KSZ8851SNL_RSTN_GPIO, KSZ8851SNL_RSTN_FLAGS);
/* Reset the Micrel in a proper state. */
while( count-- )
{
/* Perform hardware reset with respect to the reset timing from the datasheet. */
gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO);
vTaskDelay(2);
gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO);
vTaskDelay(2);
/* Init step1: read chip ID. */
dev_id = ksz8851_reg_read(REG_CHIP_ID);
if( ( dev_id & 0xFFF0 ) == CHIP_ID_8851_16 )
{
id_ok = 1;
break;
}
}
if( id_ok != 0 )
{
ksz8851snl_set_registers();
}
return id_ok ? 1 : -1;
}
