/** * \brief Test SPI setting. * * This test tests SPI reset/enable/disable. * * \param test Current test case. */ static void run_spi_ctrl_test(const struct test_case *test) { spi_enable_clock(CONF_TEST_SPI); /* Test enable */ spi_enable(CONF_TEST_SPI); test_assert_true(test, spi_is_enabled(CONF_TEST_SPI), "Test SPI enable: enable failed"); /* Test reset */ spi_reset(CONF_TEST_SPI); test_assert_true(test, !spi_is_enabled(CONF_TEST_SPI) && CONF_TEST_SPI->SPI_MR == 0 && CONF_TEST_SPI->SPI_IMR == 0 && CONF_TEST_SPI->SPI_CSR[0] == 0 && CONF_TEST_SPI->SPI_CSR[1] == 0 && CONF_TEST_SPI->SPI_CSR[2] == 0 && CONF_TEST_SPI->SPI_CSR[3] == 0 && #if SAM4L CONF_TEST_SPI->SPI_WPCR == 0, #else CONF_TEST_SPI->SPI_WPMR == 0, #endif "Test SPI reset: should have read 0"); }
/** * \brief Initialize SPI as slave. */ static void spi_slave_initialize(void) { uint32_t i; /* Reset status */ gs_spi_status.ul_total_block_number = 0; gs_spi_status.ul_total_command_number = 0; for (i = 0; i < NB_STATUS_CMD; i++) { gs_spi_status.ul_cmd_list[i] = 0; } gs_ul_spi_state = SLAVE_STATE_IDLE; gs_ul_spi_cmd = RC_SYN; puts("-I- Initialize SPI as slave \r"); /* Configure an SPI peripheral. */ spi_enable_clock(SPI_SLAVE_BASE); spi_disable(SPI_SLAVE_BASE); spi_reset(SPI_SLAVE_BASE); spi_set_slave_mode(SPI_SLAVE_BASE); spi_disable_mode_fault_detect(SPI_SLAVE_BASE); spi_set_peripheral_chip_select_value(SPI_SLAVE_BASE, SPI_CHIP_SEL); spi_set_clock_polarity(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY); spi_set_clock_phase(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE); spi_set_bits_per_transfer(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT); spi_enable_interrupt(SPI_SLAVE_BASE, SPI_IER_RDRF); spi_enable(SPI_SLAVE_BASE); /* Start waiting command. */ spi_slave_transfer(&gs_ul_spi_cmd, sizeof(gs_ul_spi_cmd)); }
/** * \internal * \brief Initialize Proxy PLC controller. * * This function will change the system clock prescaler configuration to * match the parameters. * * \note The parameters to this function are device-specific. * */ static void _pplc_if_config(void) { uint32_t ul_cpuhz; uint8_t uc_div; ul_cpuhz = sysclk_get_cpu_hz(); uc_div = ul_cpuhz / gs_ul_pplc_clock; /* Enable SPI peripheral. */ spi_enable_clock(PPLC_SPI_MODULE); /* Reset SPI */ spi_disable(PPLC_SPI_MODULE); spi_reset(PPLC_SPI_MODULE); /* Configure SPI */ spi_set_master_mode(PPLC_SPI_MODULE); spi_disable_mode_fault_detect(PPLC_SPI_MODULE); spi_set_peripheral_chip_select_value(PPLC_SPI_MODULE, PPLC_PCS); spi_set_clock_polarity(PPLC_SPI_MODULE, PPLC_CS, 0); spi_set_clock_phase(PPLC_SPI_MODULE, PPLC_CS, 1); spi_set_bits_per_transfer(PPLC_SPI_MODULE, PPLC_CS, SPI_CSR_BITS_8_BIT); spi_set_fixed_peripheral_select(PPLC_SPI_MODULE); spi_set_baudrate_div(PPLC_SPI_MODULE, PPLC_CS, uc_div); spi_set_transfer_delay(PPLC_SPI_MODULE, PPLC_CS, PPLC_DLYBS, PPLC_DLYBCT); spi_configure_cs_behavior(PPLC_SPI_MODULE, PPLC_CS, SPI_CS_RISE_NO_TX); /* Get board PPLC PDC base address and enable receiver and transmitter */ g_pplc_pdc = spi_get_pdc_base(PPLC_SPI_MODULE); spi_enable(PPLC_SPI_MODULE); }
/** Initialize the SPI peripheral * * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral * @param[out] obj The SPI object to initialize * @param[in] mosi The pin to use for MOSI * @param[in] miso The pin to use for MISO * @param[in] sclk The pin to use for SCLK */ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk) { MBED_ASSERT(obj); MBED_ASSERT(mosi !=NC && miso!=NC && sclk !=NC ); if (g_sys_init == 0) { sysclk_init(); system_board_init(); g_sys_init = 1; } Spi *sercombase = pinmap_find_sercom(mosi,miso,sclk); MBED_ASSERT(sercombase!=NC); pinmap_find_spi_info(sercombase, obj); MBED_ASSERT(obj->spi.flexcom!=NC); MBED_ASSERT(obj->spi.pdc!=NC); /* Configure SPI pins */ pin_function(mosi, pinmap_find_function(mosi, PinMap_SPI_MOSI)); ioport_disable_pin(mosi); pin_function(miso, pinmap_find_function(miso, PinMap_SPI_MISO)); ioport_disable_pin(miso); pin_function(sclk, pinmap_find_function(sclk, PinMap_SPI_SCLK)); ioport_disable_pin(sclk); #if (SAMG55) /* Enable the peripheral and set SPI mode. */ flexcom_enable(obj->spi.flexcom); flexcom_set_opmode(obj->spi.flexcom, FLEXCOM_SPI); #else /* Configure an SPI peripheral. */ spi_enable_clock(sercombase); #endif spi_disable(sercombase); spi_reset(sercombase); spi_set_lastxfer(sercombase); spi_set_master_mode(sercombase); spi_disable_mode_fault_detect(sercombase); spi_set_peripheral_chip_select_value(sercombase, SPI_CHIP_SEL); spi_set_clock_polarity(sercombase, SPI_CHIP_SEL, SPI_CLK_POLARITY); spi_set_clock_phase(sercombase, SPI_CHIP_SEL, SPI_CLK_PHASE); spi_set_bits_per_transfer(sercombase, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT); spi_set_baudrate_div(sercombase, SPI_CHIP_SEL,(sysclk_get_cpu_hz() / gSPI_clock)); spi_set_transfer_delay(sercombase, SPI_CHIP_SEL, SPI_DLYBS,SPI_DLYBCT); spi_enable(sercombase); pdc_disable_transfer(obj->spi.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS); obj->spi.spi_base=sercombase; obj->spi.cs= SPI_CHIP_SEL; obj->spi.polarity=SPI_CLK_POLARITY; obj->spi.phase=SPI_CLK_PHASE; obj->spi.transferrate=SPI_CSR_BITS_8_BIT; obj->spi.is_slave=0; }
/** * \brief Initialize SPI as master. */ static void spi_master_initialize(void) { /* Configure an SPI peripheral. */ uint32_t spi_chip_sel, spi_clk_freq, spi_clk_pol, spi_clk_pha; spi_enable_clock(SPI_MASTER_BASE); spi_reset(SPI_MASTER_BASE); spi_set_master_mode(SPI_MASTER_BASE); spi_disable_mode_fault_detect(SPI_MASTER_BASE); spi_disable_loopback(SPI_MASTER_BASE); spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, spi_get_pcs(2)); // This sets the value of PCS within the Mode Register. spi_set_variable_peripheral_select(SPI_MASTER_BASE); // PCS needs to be set within each transfer (PCS within SPI_TDR). spi_disable_peripheral_select_decode(SPI_MASTER_BASE); // Each CS is to be connected to a single device. spi_set_delay_between_chip_select(SPI_MASTER_BASE, SPI_DLYBCS); /* Set communication parameters for CS0 */ spi_chip_sel = 0; spi_clk_freq = 100000; // SPI CLK for RTC = 100kHz. spi_clk_pol = 1; spi_clk_pha = 0; spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS, SPI_DLYBCT); spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_16_BIT); spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz())); spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED); // CS rises after SPI transfers have completed. spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol); spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha); /* Set communication parameters for CS1 */ spi_chip_sel = 1; spi_clk_freq = 2000000; // SPI CLK for RTC = 4MHz. spi_clk_pol = 0; spi_clk_pha = 0; spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS, SPI_DLYBCT); spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT); spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz())); spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED); spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol); spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha); /* Set communication parameters for CS2 */ spi_chip_sel = 2; spi_clk_freq = 44000000; // SPI CLK for MEM2 = 44MHz. spi_clk_pol = 1; spi_clk_pha = 0; spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS, SPI_DLYBCT); spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT); spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz())); spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_KEEP_LOW); spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol); spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha); /* Enable SPI Communication */ spi_enable(SPI_MASTER_BASE); }
/** \brief Initialize the SPI in master mode. * * \param p_spi Base address of the SPI instance. * */ void spi_master_init(Spi *p_spi) { spi_enable_clock(p_spi); spi_reset(p_spi); spi_set_master_mode(p_spi); spi_disable_mode_fault_detect(p_spi); spi_disable_loopback(p_spi); spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID); spi_set_fixed_peripheral_select(p_spi); spi_disable_peripheral_select_decode(p_spi); spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS); }
static void _spi_init_base(Spi * spi_base) { spi_enable_clock(spi_base); spi_disable(spi_base); spi_reset(spi_base); spi_set_lastxfer(spi_base); spi_set_master_mode(spi_base); spi_disable_mode_fault_detect(spi_base); spi_set_variable_peripheral_select(spi_base); spi_enable_interrupt(_spi_base, SPI_IER_RDRF); // spi_enable_loopback(spi_base); // ?????????????????? }
/* * @fn nm_bus_init * @brief Initialize the bus wrapper * @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure */ sint8 nm_bus_init(void *pvinit) { sint8 result = M2M_SUCCESS; #ifdef CONF_WINC_USE_I2C twihs_options_t opt; /* Enable the peripheral clock for TWI */ pmc_enable_periph_clk(CONF_WINC_I2C_ID); /* Configure the options of TWI driver */ opt.master_clk = sysclk_get_peripheral_hz(); opt.speed = CONF_WINC_TWIHS_CLOCK; if (twihs_master_init(CONF_WINC_I2C, &opt) != TWIHS_SUCCESS) { M2M_ERR("-E-\tTWI master initialization failed.\r"); while (1) { /* Capture error */ } } #elif CONF_WINC_USE_SPI /* Configure SPI pins. */ ioport_set_pin_mode(CONF_WINC_SPI_MISO_GPIO, CONF_WINC_SPI_MISO_FLAGS); ioport_set_pin_mode(CONF_WINC_SPI_MOSI_GPIO, CONF_WINC_SPI_MOSI_FLAGS); ioport_set_pin_mode(CONF_WINC_SPI_CLK_GPIO, CONF_WINC_SPI_CLK_FLAGS); ioport_set_pin_mode(CONF_WINC_SPI_CS_GPIO, CONF_WINC_SPI_CS_FLAGS); ioport_disable_pin(CONF_WINC_SPI_MISO_GPIO); ioport_disable_pin(CONF_WINC_SPI_MOSI_GPIO); ioport_disable_pin(CONF_WINC_SPI_CLK_GPIO); ioport_disable_pin(CONF_WINC_SPI_CS_GPIO); spi_enable_clock(CONF_WINC_SPI); spi_disable(CONF_WINC_SPI); spi_reset(CONF_WINC_SPI); spi_set_master_mode(CONF_WINC_SPI); spi_disable_mode_fault_detect(CONF_WINC_SPI); spi_set_peripheral_chip_select_value(CONF_WINC_SPI, CONF_WINC_SPI_NPCS); spi_set_clock_polarity(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_POL); spi_set_clock_phase(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_PHA); spi_set_bits_per_transfer(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, SPI_CSR_BITS_8_BIT); spi_set_baudrate_div(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, (sysclk_get_cpu_hz() / CONF_WINC_SPI_CLOCK)); spi_set_transfer_delay(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_DLYBS, CONF_WINC_SPI_DLYBCT); spi_enable(CONF_WINC_SPI); nm_bsp_reset(); #endif return result; }
/** \brief Initialize the SPI in master mode. * * \param p_spi Base address of the SPI instance. * */ void spi_master_init(Spi *p_spi) { #if SAMG55 flexcom_enable(BOARD_FLEXCOM_SPI); flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI); #else spi_enable_clock(p_spi); #endif spi_reset(p_spi); spi_set_master_mode(p_spi); spi_disable_mode_fault_detect(p_spi); spi_disable_loopback(p_spi); spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID); spi_set_fixed_peripheral_select(p_spi); spi_disable_peripheral_select_decode(p_spi); spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS); }
/** * \brief Initialize SPI as slave. */ static void spi_slave_initialize(void) { g_uc_role = SLAVE_MODE; puts("-I- Initialize SPI as slave \r"); /* Configure an SPI peripheral. */ spi_enable_clock(SPI_SLAVE_BASE); spi_disable(SPI_SLAVE_BASE); spi_reset(SPI_SLAVE_BASE); spi_set_slave_mode(SPI_SLAVE_BASE); spi_disable_mode_fault_detect(SPI_SLAVE_BASE); spi_set_peripheral_chip_select_value(SPI_SLAVE_BASE, SPI_CHIP_PCS); spi_set_clock_polarity(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY); spi_set_clock_phase(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE); spi_set_bits_per_transfer(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT); spi_enable(SPI_SLAVE_BASE); }
/** * \brief Initialize SPI as master. */ static void radioSpiInit(void) { /* Configure an SPI peripheral. */ spi_enable_clock(SPI_MASTER_BASE); spi_disable(SPI_MASTER_BASE); spi_reset(SPI_MASTER_BASE); spi_set_lastxfer(SPI_MASTER_BASE); spi_set_master_mode(SPI_MASTER_BASE); spi_disable_mode_fault_detect(SPI_MASTER_BASE); spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_SEL); spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY); spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE); spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT); spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock)); spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT); spi_enable(SPI_MASTER_BASE); }
/* * Initialise the SPI interface as a SLAVE * */ void spi_slave_initialize(void) { NVIC_DisableIRQ(SPI_IRQn); NVIC_ClearPendingIRQ(SPI_IRQn); NVIC_SetPriority(SPI_IRQn, 0); NVIC_EnableIRQ(SPI_IRQn); /* Configure an SPI peripheral. */ spi_enable_clock(SPI_SLAVE_BASE); spi_disable(SPI_SLAVE_BASE); spi_reset(SPI_SLAVE_BASE); spi_set_slave_mode(SPI_SLAVE_BASE); spi_disable_mode_fault_detect(SPI_SLAVE_BASE); spi_set_peripheral_chip_select_value(SPI_SLAVE_BASE, SPI_CHIP_PCS); spi_set_clock_polarity(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY); spi_set_clock_phase(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE); spi_set_bits_per_transfer(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT); spi_enable_interrupt(SPI_SLAVE_BASE, SPI_IER_RDRF); spi_enable(SPI_SLAVE_BASE); }
/* * Initialise the SPI interface as a MASTER * */ void spi_master_initialize(void) { /* Configure an SPI peripheral. */ spi_enable_clock(SPI_MASTER_BASE); spi_disable(SPI_MASTER_BASE); spi_reset(SPI_MASTER_BASE); spi_set_master_mode(SPI_MASTER_BASE); spi_disable_mode_fault_detect(SPI_MASTER_BASE); spi_disable_loopback(SPI_MASTER_BASE); spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS); spi_set_fixed_peripheral_select(SPI_MASTER_BASE); spi_disable_peripheral_select_decode(SPI_MASTER_BASE); spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT); spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT); spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock)); spi_configure_cs_behavior(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CS_KEEP_LOW); spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY); spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE); spi_enable(SPI_MASTER_BASE); }
/** * \brief Initialize SPI as master. */ static void spi_master_initialize(void) { g_uc_role = MASTER_MODE; puts("-I- Initialize SPI as master\r"); /* Configure an SPI peripheral. */ spi_enable_clock(SPI_MASTER_BASE); spi_disable(SPI_MASTER_BASE); spi_reset(SPI_MASTER_BASE); spi_set_lastxfer(SPI_MASTER_BASE); spi_set_master_mode(SPI_MASTER_BASE); spi_disable_mode_fault_detect(SPI_MASTER_BASE); spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS); spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY); spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE); spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT); spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock)); spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT); spi_enable(SPI_MASTER_BASE); }
void board_init(void) { ioport_init(); //SPI interface initialization #ifdef CONF_SPI //MISO ioport_set_pin_peripheral_mode(PIN_PA21, IOPORT_MODE_MUX_A); //MOSI ioport_set_pin_peripheral_mode(PIN_PA22, IOPORT_MODE_MUX_A); //SCK ioport_set_pin_peripheral_mode(PIN_PA23, IOPORT_MODE_MUX_A); //CS0 ioport_set_pin_peripheral_mode(PIN_PA24, IOPORT_MODE_MUX_A); //CS1 ioport_set_pin_peripheral_mode(PIN_PA13, IOPORT_MODE_MUX_C); //CS2 ioport_set_pin_peripheral_mode(PIN_PA14, IOPORT_MODE_MUX_C); //CS3 ioport_set_pin_peripheral_mode(PIN_PB12, IOPORT_MODE_MUX_B); spi_enable_clock(SPI); spi_disable(SPI); spi_reset(SPI); spi_set_master_mode(SPI); spi_disable_mode_fault_detect(SPI); spi_disable_loopback(SPI); spi_set_variable_peripheral_select(SPI); spi_disable_peripheral_select_decode(SPI); //spi_set_peripheral_chip_select_value(SPI, SPI_CHSEL); //spi_set_transfer_delay(SPI, 1, 50, 0); //spi_set_delay_between_chip_select(SPI, 0); for(char i = 0; i < 4; i++){ spi_set_bits_per_transfer(SPI, i, 8); //spi_set_baudrate_div(SPI, i, spi_calc_baudrate_div(1000000, sysclk_get_cpu_hz())); spi_set_baudrate_div(SPI, i, (sysclk_get_cpu_hz() / 500000)); spi_configure_cs_behavior(SPI, i, SPI_CS_KEEP_LOW); spi_set_clock_polarity(SPI, i, 0); spi_set_clock_phase(SPI, i, 0); } spi_enable(SPI); #endif //USART0 initialization #ifdef CONF_USART0 //USART0 RXD ioport_set_pin_peripheral_mode(PIN_PA11, IOPORT_MODE_MUX_A); #if SAM4L sysclk_enable_peripheral_clock(USART0); #endif //USART0 configuration struct const sam_usart_opt_t usart0_console_settings = { CONF_USART_0_BAUDRATE, CONF_USART_0_CHAR_LENGTH, CONF_USART_0_PARITY, CONF_USART_0_STOP_BITS, US_MR_CHMODE_NORMAL }; usart_init_rs232(USART0, &usart0_console_settings, sysclk_get_main_hz()); usart_enable_tx(USART0); usart_enable_rx(USART0); usart_enable_interrupt(USART0, US_IER_RXRDY); NVIC_SetPriority(USART0_IRQn, 10); NVIC_EnableIRQ(USART0_IRQn); #endif //USART1 initialization #ifdef CONF_USART1 //USART1 TXD ioport_set_pin_peripheral_mode(PIN_PA16, IOPORT_MODE_MUX_A); //USART1 RXD ioport_set_pin_peripheral_mode(PIN_PA15, IOPORT_MODE_MUX_A); #if SAM4L sysclk_enable_peripheral_clock(USART1); #endif //USART1 configuration struct const sam_usart_opt_t usart1_console_settings = { CONF_USART_1_BAUDRATE, CONF_USART_1_CHAR_LENGTH, CONF_USART_1_PARITY, CONF_USART_1_STOP_BITS, US_MR_CHMODE_NORMAL }; usart_init_rs232(USART1, &usart1_console_settings, sysclk_get_main_hz()); usart_enable_tx(USART1); usart_enable_rx(USART1); usart_enable_interrupt(USART1, US_IER_RXRDY); //NVIC_SetPriority(USART0_IRQn, 10); NVIC_EnableIRQ(USART1_IRQn); #endif #ifdef CONF_TWIMS1 //SDA ioport_set_pin_peripheral_mode(PIN_PB00, IOPORT_MODE_MUX_A); //SCL ioport_set_pin_peripheral_mode(PIN_PB01, IOPORT_MODE_MUX_A); /* Set TWIM options */ uint32_t cpu_speed = 0; cpu_speed = sysclk_get_peripheral_bus_hz(EXAMPLE_TWIM); struct twim_config opts = { .twim_clk = sysclk_get_cpu_hz(), //Importante .speed = TWIM_MASTER_SPEED, .hsmode_speed = 0, .data_setup_cycles = 0, .hsmode_data_setup_cycles = 0, .smbus = false, .clock_slew_limit = 0, .clock_drive_strength_low = 0, .data_slew_limit = 0, .data_drive_strength_low = 0, .hs_clock_slew_limit = 0, .hs_clock_drive_strength_high = 0, .hs_clock_drive_strength_low = 0, .hs_data_slew_limit = 0, .hs_data_drive_strength_low = 0, }; /* Initialize the TWIM Module */ twim_set_callback(EXAMPLE_TWIM, 0, twim_default_callback, 1); twim_set_config(EXAMPLE_TWIM, &opts); #endif //ADS 1294R initialization #ifdef CONF_ADS ADS_ioconfig(); Soft_Reset_ADS1298(); delay_us(50); Stop_Read_Data_Continuous(); /*Configuration register 1*/ ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_1_REGISTER , SINGLE_BYTE); ADS1298_SPI_Data(0x06); /*Configuration register 2*/ ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_2_REGISTER , SINGLE_BYTE); ADS1298_SPI_Data(0x00); /*Configuration register 3*/ ADS1298_SPI_Address_Byte_Count(WRITE_CONFIG_3_REGISTER , SINGLE_BYTE); ADS1298_SPI_Data(0xDC); /*Channel 1 register*/ ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_1_SET_REGISTER, SINGLE_BYTE); ADS1298_SPI_Data(0x00); /*Channel 2 register*/ ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_2_SET_REGISTER , SINGLE_BYTE); ADS1298_SPI_Data(0x00); /*Channel 3 register*/ ADS1298_SPI_Address_Byte_Count(WRITE_CHANNEL_3_SET_REGISTER , SINGLE_BYTE); ADS1298_SPI_Data(0x00); /*RLD_SENSP register*/ ADS1298_SPI_Address_Byte_Count(WRITE_RIGHT_LEG_DRIVE_SENSE_POSITIVE_REGISTER, SINGLE_BYTE); ADS1298_SPI_Data(0x0F); /*RLD_SENSN register*/ ADS1298_SPI_Address_Byte_Count(WRITE_RIGHT_LEG_DRIVE_SENSE_NEGATIVE_REGISTER, SINGLE_BYTE); ADS1298_SPI_Data(0x0F); /*Respiration control register*/ //Respiration channel not enabled #endif }
/** * \brief KSZ8851SNL initialization function. * * \return 0 on success, 1 on communication error. */ uint32_t ksz8851snl_init(void) { uint32_t count = 0; uint16_t dev_id = 0; /* Configure the SPI peripheral. */ spi_enable_clock(KSZ8851SNL_SPI); spi_disable(KSZ8851SNL_SPI); spi_reset(KSZ8851SNL_SPI); spi_set_master_mode(KSZ8851SNL_SPI); spi_disable_mode_fault_detect(KSZ8851SNL_SPI); spi_set_peripheral_chip_select_value(KSZ8851SNL_SPI, ~(uint32_t)(1 << KSZ8851SNL_CS_PIN)); spi_set_clock_polarity(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_POLARITY); spi_set_clock_phase(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_PHASE); spi_set_bits_per_transfer(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CSR_BITS_8_BIT); spi_set_baudrate_div(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, (sysclk_get_cpu_hz() / KSZ8851SNL_CLOCK_SPEED)); spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, CONFIG_SPI_MASTER_DELAY_BS, CONFIG_SPI_MASTER_DELAY_BCT); spi_enable(KSZ8851SNL_SPI); /* Get pointer to UART PDC register base. */ g_p_spi_pdc = spi_get_pdc_base(KSZ8851SNL_SPI); pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); /* Control RSTN and CSN pin from the driver. */ gpio_configure_pin(KSZ8851SNL_CSN_GPIO, KSZ8851SNL_CSN_FLAGS); gpio_set_pin_high(KSZ8851SNL_CSN_GPIO); gpio_configure_pin(KSZ8851SNL_RSTN_GPIO, KSZ8851SNL_RSTN_FLAGS); /* Reset the Micrel in a proper state. */ do { /* Perform hardware reset with respect to the reset timing from the datasheet. */ gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO); delay_ms(100); gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO); delay_ms(100); /* Init step1: read chip ID. */ dev_id = ksz8851_reg_read(REG_CHIP_ID); if (++count > 10) return 1; } while ((dev_id & 0xFFF0) != CHIP_ID_8851_16); /* Init step2-4: write QMU MAC address (low, middle then high). */ ksz8851_reg_write(REG_MAC_ADDR_0, (ETHERNET_CONF_ETHADDR4 << 8) | ETHERNET_CONF_ETHADDR5); ksz8851_reg_write(REG_MAC_ADDR_2, (ETHERNET_CONF_ETHADDR2 << 8) | ETHERNET_CONF_ETHADDR3); ksz8851_reg_write(REG_MAC_ADDR_4, (ETHERNET_CONF_ETHADDR0 << 8) | ETHERNET_CONF_ETHADDR1); /* Init step5: enable QMU Transmit Frame Data Pointer Auto Increment. */ ksz8851_reg_write(REG_TX_ADDR_PTR, ADDR_PTR_AUTO_INC); /* Init step6: configure QMU transmit control register. */ ksz8851_reg_write(REG_TX_CTRL, TX_CTRL_ICMP_CHECKSUM | TX_CTRL_UDP_CHECKSUM | TX_CTRL_TCP_CHECKSUM | TX_CTRL_IP_CHECKSUM | TX_CTRL_FLOW_ENABLE | TX_CTRL_PAD_ENABLE | TX_CTRL_CRC_ENABLE ); /* Init step7: enable QMU Receive Frame Data Pointer Auto Increment. */ ksz8851_reg_write(REG_RX_ADDR_PTR, ADDR_PTR_AUTO_INC); /* Init step8: configure QMU Receive Frame Threshold for one frame. */ ksz8851_reg_write(REG_RX_FRAME_CNT_THRES, 1); /* Init step9: configure QMU receive control register1. */ ksz8851_reg_write(REG_RX_CTRL1, RX_CTRL_UDP_CHECKSUM | RX_CTRL_TCP_CHECKSUM | RX_CTRL_IP_CHECKSUM | RX_CTRL_MAC_FILTER | RX_CTRL_FLOW_ENABLE | RX_CTRL_BROADCAST | RX_CTRL_ALL_MULTICAST| RX_CTRL_UNICAST); /* Init step10: configure QMU receive control register2. */ ksz8851_reg_write(REG_RX_CTRL2, RX_CTRL_IPV6_UDP_NOCHECKSUM | RX_CTRL_UDP_LITE_CHECKSUM | RX_CTRL_ICMP_CHECKSUM | RX_CTRL_BURST_LEN_FRAME); /* Init step11: configure QMU receive queue: trigger INT and auto-dequeue frame. */ ksz8851_reg_write(REG_RXQ_CMD, RXQ_CMD_CNTL); /* Init step12: adjust SPI data output delay. */ ksz8851_reg_write(REG_BUS_CLOCK_CTRL, BUS_CLOCK_166 | BUS_CLOCK_DIVIDEDBY_1); /* Init step13: restart auto-negotiation. */ ksz8851_reg_setbits(REG_PORT_CTRL, PORT_AUTO_NEG_RESTART); /* Init step13.1: force link in half duplex if auto-negotiation failed. */ if ((ksz8851_reg_read(REG_PORT_CTRL) & PORT_AUTO_NEG_RESTART) != PORT_AUTO_NEG_RESTART) { ksz8851_reg_clrbits(REG_PORT_CTRL, PORT_FORCE_FULL_DUPLEX); } /* Init step14: clear interrupt status. */ ksz8851_reg_write(REG_INT_STATUS, 0xFFFF); /* Init step15: set interrupt mask. */ ksz8851_reg_write(REG_INT_MASK, INT_RX); /* Init step16: enable QMU Transmit. */ ksz8851_reg_setbits(REG_TX_CTRL, TX_CTRL_ENABLE); /* Init step17: enable QMU Receive. */ ksz8851_reg_setbits(REG_RX_CTRL1, RX_CTRL_ENABLE); return 0; }
/** * \brief KSZ8851SNL initialization function. * * \return 0 on success, 1 on communication error. */ uint32_t ksz8851snl_init(void) { uint32_t count = 10; uint16_t dev_id = 0; uint8_t id_ok = 0; /* Configure the SPI peripheral. */ spi_enable_clock(KSZ8851SNL_SPI); spi_disable(KSZ8851SNL_SPI); spi_reset(KSZ8851SNL_SPI); spi_set_master_mode(KSZ8851SNL_SPI); spi_disable_mode_fault_detect(KSZ8851SNL_SPI); spi_set_peripheral_chip_select_value(KSZ8851SNL_SPI, ~(uint32_t)(1UL << KSZ8851SNL_CS_PIN)); spi_set_fixed_peripheral_select(KSZ8851SNL_SPI); //spi_disable_peripheral_select_decode(KSZ8851SNL_SPI); spi_set_clock_polarity(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_POLARITY); spi_set_clock_phase(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_PHASE); spi_set_bits_per_transfer(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CSR_BITS_8_BIT); spi_set_baudrate_div(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, (sysclk_get_cpu_hz() / KSZ8851SNL_CLOCK_SPEED)); // spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, CONFIG_SPI_MASTER_DELAY_BS, // CONFIG_SPI_MASTER_DELAY_BCT); spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, 0, 0); spi_enable(KSZ8851SNL_SPI); /* Get pointer to UART PDC register base. */ g_p_spi_pdc = spi_get_pdc_base(KSZ8851SNL_SPI); pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN); /* Control RSTN and CSN pin from the driver. */ gpio_configure_pin(KSZ8851SNL_CSN_GPIO, KSZ8851SNL_CSN_FLAGS); gpio_set_pin_high(KSZ8851SNL_CSN_GPIO); gpio_configure_pin(KSZ8851SNL_RSTN_GPIO, KSZ8851SNL_RSTN_FLAGS); /* Reset the Micrel in a proper state. */ while( count-- ) { /* Perform hardware reset with respect to the reset timing from the datasheet. */ gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO); vTaskDelay(2); gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO); vTaskDelay(2); /* Init step1: read chip ID. */ dev_id = ksz8851_reg_read(REG_CHIP_ID); if( ( dev_id & 0xFFF0 ) == CHIP_ID_8851_16 ) { id_ok = 1; break; } } if( id_ok != 0 ) { ksz8851snl_set_registers(); } return id_ok ? 1 : -1; }
/* * Configure the SPI hardware, including SPI clock speed, mode, delays, chip select pins * It uses values listed in */ void AJ_WSL_SPI_InitializeSPIController(void) { uint32_t config; /* Initialize and enable DMA controller. */ pmc_enable_periph_clk(ID_DMAC); dmac_init(DMAC); dmac_set_priority_mode(DMAC, DMAC_PRIORITY_ROUND_ROBIN); dmac_enable(DMAC); /* Configure DMA TX channel. */ config = 0; config |= DMAC_CFG_DST_PER(AJ_SPI_TX_INDEX) | DMAC_CFG_DST_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG; dmac_channel_set_configuration(DMAC, AJ_DMA_TX_CHANNEL, config); /* Configure DMA RX channel. */ config = 0; config |= DMAC_CFG_SRC_PER(AJ_SPI_RX_INDEX) | DMAC_CFG_SRC_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG; dmac_channel_set_configuration(DMAC, AJ_DMA_RX_CHANNEL, config); /* Enable receive channel interrupt for DMAC. */ uint8_t* interruptEnableAddress = AJ_SPI_ISER1_IEN_ADDR; *interruptEnableAddress = AJ_SPI_DMAC_IEN_BIT; dmac_enable_interrupt(DMAC, (1 << AJ_DMA_RX_CHANNEL)); dmac_enable_interrupt(DMAC, (1 << AJ_DMA_TX_CHANNEL)); //AJ_WSL_DMA_Setup(); dmac_channel_disable(DMAC, AJ_DMA_TX_CHANNEL); dmac_channel_disable(DMAC, AJ_DMA_RX_CHANNEL); /* * Configure the hardware to enable SPI and some output pins */ { pmc_enable_periph_clk(ID_PIOA); pmc_enable_periph_clk(ID_PIOB); pmc_enable_periph_clk(ID_PIOC); pmc_enable_periph_clk(ID_PIOD); // make all of these pins controlled by the right I/O controller pio_configure_pin_group(PIOA, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_A); pio_configure_pin_group(PIOB, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_B); pio_configure_pin_group(PIOC, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_C); pio_configure_pin_group(PIOD, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_D); /* * Reset the device by toggling the CHIP_POWER */ ioport_set_pin_dir(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_DIR_OUTPUT); ioport_set_pin_level(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_PIN_LEVEL_LOW); AJ_Sleep(10); ioport_set_pin_level(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_PIN_LEVEL_HIGH); /* * Reset the device by toggling the CHIP_PWD# signal */ ioport_set_pin_dir(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_DIR_OUTPUT); ioport_set_pin_level(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_PIN_LEVEL_LOW); AJ_Sleep(10); ioport_set_pin_level(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_PIN_LEVEL_HIGH); /* configure the pin that detects SPI data ready from the target chip */ ioport_set_pin_dir(AJ_WSL_SPI_CHIP_SPI_INT_PIN, IOPORT_DIR_INPUT); ioport_set_pin_sense_mode(AJ_WSL_SPI_CHIP_SPI_INT_PIN, IOPORT_SENSE_LEVEL_LOW); pio_handler_set(PIOC, ID_PIOC, AJ_WSL_SPI_CHIP_SPI_INT_BIT, (PIO_PULLUP | PIO_IT_FALL_EDGE), &AJ_WSL_SPI_CHIP_SPI_ISR); pio_handler_set_priority(PIOD, (IRQn_Type) ID_PIOC, 0xB); pio_enable_interrupt(PIOC, AJ_WSL_SPI_CHIP_SPI_INT_BIT); } spi_enable_clock(AJ_WSL_SPI_DEVICE); spi_reset(AJ_WSL_SPI_DEVICE); spi_set_lastxfer(AJ_WSL_SPI_DEVICE); spi_set_master_mode(AJ_WSL_SPI_DEVICE); spi_disable_mode_fault_detect(AJ_WSL_SPI_DEVICE); spi_set_peripheral_chip_select_value(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS); spi_set_clock_polarity(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_CLOCK_POLARITY); spi_set_clock_phase(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_CLOCK_PHASE); spi_set_bits_per_transfer(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, SPI_CSR_BITS_8_BIT); spi_set_baudrate_div(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, (sysclk_get_cpu_hz() / AJ_WSL_SPI_CLOCK_RATE)); spi_set_transfer_delay(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_DELAY_BEFORE_CLOCK, AJ_WSL_SPI_DELAY_BETWEEN_TRANSFERS); spi_set_fixed_peripheral_select(AJ_WSL_SPI_DEVICE); spi_configure_cs_behavior(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, SPI_CS_RISE_FORCED); spi_enable_interrupt(AJ_WSL_SPI_DEVICE, SPI_IER_TDRE | SPI_IER_RDRF); spi_enable(AJ_WSL_SPI_DEVICE); }
// Here should be all the initialization functions for the module before 12v power void init_module_peripherals_bp(void) { /* LEDs IO */ pmc_enable_periph_clk(IN_CLK_LED1_PIO_ID); ioport_set_pin_dir(IN_CLK_LED1_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(IN_CLK_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(IN_CLK_LED2_PIO_ID); ioport_set_pin_dir(IN_CLK_LED2_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(IN_CLK_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(IN_CLK_LED3_PIO_ID); ioport_set_pin_dir(IN_CLK_LED3_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(IN_CLK_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(IN_DAT_LED1_PIO_ID); ioport_set_pin_dir(IN_DAT_LED1_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(IN_DAT_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(IN_DAT_LED2_PIO_ID); ioport_set_pin_dir(IN_DAT_LED2_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(IN_DAT_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(IN_DAT_LED3_PIO_ID); ioport_set_pin_dir(IN_DAT_LED3_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(IN_DAT_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(OUT_CH1_CH2_LED1_PIO_ID); ioport_set_pin_dir(OUT_CH1_CH2_LED1_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(OUT_CH1_CH2_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(OUT_CH1_CH2_LED2_PIO_ID); ioport_set_pin_dir(OUT_CH1_CH2_LED2_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(OUT_CH1_CH2_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(OUT_CH1_CH2_LED3_PIO_ID); ioport_set_pin_dir(OUT_CH1_CH2_LED3_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(OUT_CH1_CH2_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(OUT_CH3_LED1_PIO_ID); ioport_set_pin_dir(OUT_CH3_LED1_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(OUT_CH3_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(OUT_CH3_LED2_PIO_ID); ioport_set_pin_dir(OUT_CH3_LED2_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(OUT_CH3_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH); pmc_enable_periph_clk(OUT_CH3_LED3_PIO_ID); ioport_set_pin_dir(OUT_CH3_LED3_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(OUT_CH3_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH); /* Pulse inputs/state & d reset output */ pmc_enable_periph_clk(OUT_PULSE_DET_PIO_ID); ioport_set_pin_dir(OUT_PULSE_DET_GPIO, IOPORT_DIR_INPUT); pmc_enable_periph_clk(DATA_IN_DET_PIO_ID); ioport_set_pin_dir(DATA_IN_DET_GPIO, IOPORT_DIR_INPUT); pmc_enable_periph_clk(CLK_IN_DET_PIO_ID); ioport_set_pin_dir(CLK_IN_DET_GPIO, IOPORT_DIR_INPUT); pmc_enable_periph_clk(OUT_PULSE_STATE_PIO_ID); ioport_set_pin_dir(OUT_PULSE_STATE_GPIO, IOPORT_DIR_INPUT); pmc_enable_periph_clk(DATA_IN_STATE_PIO_ID); ioport_set_pin_dir(DATA_IN_STATE_GPIO, IOPORT_DIR_INPUT); pmc_enable_periph_clk(CLK_IN_STATE_PIO_ID); ioport_set_pin_dir(CLK_IN_STATE_GPIO, IOPORT_DIR_INPUT); pmc_enable_periph_clk(OUT_PULSE_RST_PIO_ID); ioport_set_pin_dir(OUT_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(OUT_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW); pmc_enable_periph_clk(DATA_PULSE_RST_PIO_ID); ioport_set_pin_dir(DATA_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(DATA_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW); pmc_enable_periph_clk(CLK_PULSE_RST_PIO_ID); ioport_set_pin_dir(CLK_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(CLK_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW); /* Sload */ pmc_enable_periph_clk(DATA_DELAY_SLOAD_PIO_ID); ioport_set_pin_dir(DATA_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(DATA_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW); pmc_enable_periph_clk(CLOCK_DELAY_SLOAD_PIO_ID); ioport_set_pin_dir(CLOCK_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(CLOCK_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW); pmc_enable_periph_clk(RESET_DELAY_SLOAD_PIO_ID); ioport_set_pin_dir(RESET_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(RESET_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW); pmc_enable_periph_clk(RF_ATTEN_SLOAD_PIO_ID); ioport_set_pin_dir(RF_ATTEN_SLOAD_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(RF_ATTEN_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW); /* Delay enables */ pmc_enable_periph_clk(DATA_DELAY_EN_PIO_ID); ioport_set_pin_dir(DATA_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(DATA_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014) pmc_enable_periph_clk(CLOCK_DELAY_EN_PIO_ID); ioport_set_pin_dir(CLOCK_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(CLOCK_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014) pmc_enable_periph_clk(RESET_DELAY_EN_PIO_ID); ioport_set_pin_dir(RESET_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT); ioport_set_pin_level(RESET_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014) // Init LED interrupt, uint32_t ul_div; uint32_t ul_tcclks; /* Get system clock. */ uint32_t ul_sysclk = sysclk_get_cpu_hz(); /* Configure PMC. */ pmc_enable_periph_clk(ID_TC1); /* Configure TC for a TC_FREQ frequency and trigger on RC compare. */ tc_find_mck_divisor(20, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk); tc_init(TC0, 1, ul_tcclks | TC_CMR_CPCTRG); tc_write_rc(TC0, 1, (ul_sysclk / ul_div) / 20); /* Configure and enable interrupt on RC compare. */ tc_start(TC0, 1); NVIC_DisableIRQ(TC1_IRQn); NVIC_ClearPendingIRQ(TC1_IRQn); //NVIC_SetPriority(TC1_IRQn, 0); NVIC_EnableIRQ((IRQn_Type)ID_TC1); tc_enable_interrupt(TC0, 1, TC_IER_CPCS); /* SPI interface */ gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS); gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS); gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS); //gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); // Controled by software /* Configure an SPI peripheral. */ spi_enable_clock(SPI0); spi_disable(SPI0); spi_reset(SPI0); spi_set_lastxfer(SPI0); spi_set_master_mode(SPI0); spi_disable_mode_fault_detect(SPI0); /* Set variable chip select */ spi_set_variable_peripheral_select(SPI0); /* Configure delay SPI channel */ spi_set_clock_polarity(SPI0, SPI_CHIP_SEL, SPI_CLK_POLARITY); spi_set_clock_phase(SPI0, SPI_CHIP_SEL, SPI_CLK_PHASE); spi_set_bits_per_transfer(SPI0, SPI_CHIP_SEL, SPI_CSR_BITS_11_BIT); spi_configure_cs_behavior(SPI0, SPI_CHIP_SEL, SPI_CS_RISE_FORCED); spi_set_baudrate_div(SPI0, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock)); spi_set_transfer_delay(SPI0, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT); /* Configure RF atten SPI channel */ spi_set_clock_polarity(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_POLARITY); spi_set_clock_phase(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_PHASE); spi_set_bits_per_transfer(SPI0, SPI_ALT_CHIP_SEL, SPI_CSR_BITS_16_BIT); spi_configure_cs_behavior(SPI0, SPI_ALT_CHIP_SEL, SPI_CS_RISE_FORCED); spi_set_baudrate_div(SPI0, SPI_ALT_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock)); spi_set_transfer_delay(SPI0, SPI_ALT_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT); /* Enable SPI */ spi_enable(SPI0); }