/*! \brief Initializes the SPI in master mode. * * \param spi Base address of the SPI instance. * */ void spi_master_init(SPI_t *spi) { #ifdef SPIA if((uint16_t)spi == (uint16_t)&SPIA) { sysclk_enable_module(SYSCLK_PORT_A,PR_SPI_bm); } #endif #ifdef SPIB if((uint16_t)spi == (uint16_t)&SPIB) { sysclk_enable_module(SYSCLK_PORT_B,PR_SPI_bm); } #endif #ifdef SPIC if((uint16_t)spi == (uint16_t)&SPIC) { sysclk_enable_module(SYSCLK_PORT_C,PR_SPI_bm); } #endif #ifdef SPID if((uint16_t)spi == (uint16_t)&SPID) { sysclk_enable_module(SYSCLK_PORT_D,PR_SPI_bm); } #endif #ifdef SPIE if((uint16_t)spi == (uint16_t)&SPIE) { sysclk_enable_module(SYSCLK_PORT_E,PR_SPI_bm); } #endif #ifdef SPIF if((uint16_t)spi == (uint16_t)&SPIF) { sysclk_enable_module(SYSCLK_PORT_F,PR_SPI_bm); } #endif spi_enable_master_mode(spi); }
/** * \brief Initializes the SPI in master mode. * * \param spi Base address of the SPI instance. * */ void spi_master_init(volatile void *spi) { sysclk_enable_module(POWER_RED_REG0, PRSPI_bm); spi_enable_master_mode(spi); }
void SPI_Init(void) { spi_xmega_set_baud_div(&NRF24L01_L_SPI,8000000UL,F_CPU); spi_enable_master_mode(&NRF24L01_L_SPI); spi_enable(&NRF24L01_L_SPI); }
int main (void) { En_RC32M(); PORT_init(); TimerD0_init(); PMIC_CTRL |=PMIC_LOLVLEN_bm|PMIC_MEDLVLEN_bm; wdt_enable(); USART_R_init(); USART_L_init(); USARTD0_init(); NRF24L01_L_CE_LOW; //disable transceiver modes NRF24L01_R_CE_LOW; ///////////////////////////////////////////////////////////////////////////////////////////spi se spi_xmega_set_baud_div(&NRF24L01_L_SPI,8000000UL,F_CPU); spi_enable_master_mode(&NRF24L01_L_SPI); spi_enable(&NRF24L01_L_SPI); spi_xmega_set_baud_div(&NRF24L01_R_SPI,8000000UL,F_CPU); spi_enable_master_mode(&NRF24L01_R_SPI); spi_enable(&NRF24L01_R_SPI); sei(); ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// _delay_us(10); _delay_ms(100); //power on reset delay needs 100ms NRF24L01_L_Clear_Interrupts(); NRF24L01_R_Clear_Interrupts(); NRF24L01_L_Flush_TX(); NRF24L01_R_Flush_TX(); NRF24L01_L_Flush_RX(); NRF24L01_R_Flush_RX(); NRF24L01_L_CE_LOW; NRF24L01_L_Init_milad(_RX_MODE, _CH_L, _2Mbps, Address, _Address_Width, _Buffer_Size, RF_PWR_MAX); NRF24L01_L_WriteReg(W_REGISTER | DYNPD,0x07);//0x07 NRF24L01_L_WriteReg(W_REGISTER | FEATURE,0x06);//0x06 NRF24L01_L_CE_HIGH; NRF24L01_R_CE_LOW; NRF24L01_R_Init_milad(_RX_MODE, _CH_R, _2Mbps, Address, _Address_Width, _Buffer_Size, RF_PWR_MAX); NRF24L01_R_WriteReg(W_REGISTER | DYNPD,0x07); NRF24L01_R_WriteReg(W_REGISTER | FEATURE,0x06); NRF24L01_R_CE_HIGH; _delay_us(130); for (uint8_t i=0;i<Max_Robot;i++) { Robot_D_tmp[i].RID=12; } while (1) { //Buf_Tx_R[7][7] = 0xFF; //Buf_Tx_R[7][8] = 0X01; for(uint8_t i=0;i<12;i++) { Buf_Tx_R[i][11] = Menu_Num; Buf_Tx_R[i][12] = (int)(kp*100); Buf_Tx_R[i][13] = (int)(ki*100); Buf_Tx_R[i][14] = (int)(kd*100); } _delay_us(1); } }