/** Initialize the SPI peripheral
*
* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
* @param[out] obj The SPI object to initialize
* @param[in] mosi The pin to use for MOSI
* @param[in] miso The pin to use for MISO
* @param[in] sclk The pin to use for SCLK
*/
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk)
{
MBED_ASSERT(obj);
MBED_ASSERT(mosi !=NC && miso!=NC && sclk !=NC );
if (g_sys_init == 0) {
sysclk_init();
system_board_init();
g_sys_init = 1;
}
Spi *sercombase = pinmap_find_sercom(mosi,miso,sclk);
MBED_ASSERT(sercombase!=NC);
pinmap_find_spi_info(sercombase, obj);
MBED_ASSERT(obj->spi.flexcom!=NC);
MBED_ASSERT(obj->spi.pdc!=NC);
/* Configure SPI pins */
pin_function(mosi, pinmap_find_function(mosi, PinMap_SPI_MOSI));
ioport_disable_pin(mosi);
pin_function(miso, pinmap_find_function(miso, PinMap_SPI_MISO));
ioport_disable_pin(miso);
pin_function(sclk, pinmap_find_function(sclk, PinMap_SPI_SCLK));
ioport_disable_pin(sclk);
#if (SAMG55)
/* Enable the peripheral and set SPI mode. */
flexcom_enable(obj->spi.flexcom);
flexcom_set_opmode(obj->spi.flexcom, FLEXCOM_SPI);
#else
/* Configure an SPI peripheral. */
spi_enable_clock(sercombase);
#endif
spi_disable(sercombase);
spi_reset(sercombase);
spi_set_lastxfer(sercombase);
spi_set_master_mode(sercombase);
spi_disable_mode_fault_detect(sercombase);
spi_set_peripheral_chip_select_value(sercombase, SPI_CHIP_SEL);
spi_set_clock_polarity(sercombase, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(sercombase, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(sercombase, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(sercombase, SPI_CHIP_SEL,(sysclk_get_cpu_hz() / gSPI_clock));
spi_set_transfer_delay(sercombase, SPI_CHIP_SEL, SPI_DLYBS,SPI_DLYBCT);
spi_enable(sercombase);
pdc_disable_transfer(obj->spi.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);
obj->spi.spi_base=sercombase;
obj->spi.cs= SPI_CHIP_SEL;
obj->spi.polarity=SPI_CLK_POLARITY;
obj->spi.phase=SPI_CLK_PHASE;
obj->spi.transferrate=SPI_CSR_BITS_8_BIT;
obj->spi.is_slave=0;
}
/**
* \brief Deselect the given device on the SPI bus.
*
* Call board chip deselect.
*
* \param p_spi Base address of the SPI instance.
* \param device SPI device.
*
* \pre SPI device must be selected with spi_select_device() first.
*/
void spi_deselect_device(Spi *p_spi, struct spi_device *device)
{
device = device;
while (!spi_is_tx_empty(p_spi)) {
}
// Assert all lines; no peripheral is selected.
spi_set_peripheral_chip_select_value(p_spi, NONE_CHIP_SELECT_ID);
// Last transfer, so de-assert the current NPCS if CSAAT is set.
spi_set_lastxfer(p_spi);
}
static void _spi_init_base(Spi * spi_base)
{
spi_enable_clock(spi_base);
spi_disable(spi_base);
spi_reset(spi_base);
spi_set_lastxfer(spi_base);
spi_set_master_mode(spi_base);
spi_disable_mode_fault_detect(spi_base);
spi_set_variable_peripheral_select(spi_base);
spi_enable_interrupt(_spi_base, SPI_IER_RDRF);
// spi_enable_loopback(spi_base); // ??????????????????
}
/**
* \brief Deselect the given device on the SPI bus.
*
* Call board chip deselect.
*
* \param p_spi Base address of the SPI instance.
* \param device SPI device.
*
* \pre SPI device must be selected with spi_select_device() first.
*/
void spi_deselect_device(Spi *p_spi, const struct spi_device *device)
{
uint32_t timeout = SPI_TIMEOUT;
while (!spi_is_tx_empty(p_spi)) {
if (!timeout--) {
return;
}
}
// Last transfer, so de-assert the current NPCS if CSAAT is set.
spi_set_lastxfer(p_spi);
// Disable the CS line
digitalWrite(device->cs, HIGH);
// Assert all lines; no peripheral is selected.
spi_set_peripheral_chip_select_value(p_spi, NONE_CHIP_SELECT_ID);
}
/**
* \brief Initialize SPI as master.
*/
static void radioSpiInit(void)
{
/* Configure an SPI peripheral. */
spi_enable_clock(SPI_MASTER_BASE);
spi_disable(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_lastxfer(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_SEL);
spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL,
(sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS,
SPI_DLYBCT);
spi_enable(SPI_MASTER_BASE);
}
platform_result_t platform_spi_init( const platform_spi_t* spi, const platform_spi_config_t* config )
{
UNUSED_PARAMETER(spi);
UNUSED_PARAMETER(config);
platform_mcu_powersave_disable( );
Pdc* spi_pdc = spi_get_pdc_base( spi->peripheral );
/* Setup chip select pin */
platform_gpio_init( config->chip_select, OUTPUT_PUSH_PULL );
platform_gpio_output_high( config->chip_select );
/* Setup other pins */
platform_gpio_peripheral_pin_init( spi->mosi_pin, ( IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP ) );
platform_gpio_peripheral_pin_init( spi->miso_pin, ( IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP ) );
platform_gpio_peripheral_pin_init( spi->clk_pin, ( IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP ) );
/* Configure an SPI peripheral. */
pmc_enable_periph_clk( spi->peripheral_id );
spi_disable( spi->peripheral );
spi_reset( spi->peripheral );
spi_set_lastxfer( spi->peripheral );
spi_set_master_mode( spi->peripheral );
spi_disable_mode_fault_detect( spi->peripheral );
spi_set_peripheral_chip_select_value( spi->peripheral, 0 );
spi_set_clock_polarity( spi->peripheral, 0, ( ( config->mode && SPI_CLOCK_IDLE_HIGH ) ? (1) : (0) ) );
spi_set_clock_phase( spi->peripheral, 0, ( ( config->mode && SPI_CLOCK_RISING_EDGE ) ? (1) : (0) ) );
spi_set_bits_per_transfer( spi->peripheral, 0, SPI_CSR_BITS_8_BIT );
spi_set_baudrate_div( spi->peripheral, 0, (uint8_t)( CPU_CLOCK_HZ / config->speed ) );
spi_set_transfer_delay( spi->peripheral, 0, 0, 0 );
spi_enable( spi->peripheral );
pdc_disable_transfer( spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS );
platform_mcu_powersave_enable( );
return PLATFORM_SUCCESS;
}
/**
* \brief Initialize SPI as master.
*/
static void spi_master_initialize(void)
{
uint32_t i;
puts("-I- Initialize SPI as master\r");
for (i = 0; i < COMM_BUFFER_SIZE; i++) {
gs_uc_spi_m_tbuffer[i] = i;
}
/* Get pointer to SPI master PDC register base */
g_p_spim_pdc = spi_get_pdc_base(SPI_MASTER_BASE);
#if (SAMG55)
/* Enable the peripheral and set SPI mode. */
flexcom_enable(BOARD_FLEXCOM_SPI);
flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
#else
/* Configure an SPI peripheral. */
pmc_enable_periph_clk(SPI_ID);
#endif
spi_disable(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_lastxfer(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_SEL);
spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL,
SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL,
(sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS,
SPI_DLYBCT);
spi_enable(SPI_MASTER_BASE);
pdc_disable_transfer(g_p_spim_pdc, PERIPH_PTCR_RXTDIS |
PERIPH_PTCR_TXTDIS);
}
/**
* \brief Initialize SPI as master.
*/
static void spi_master_initialize(void)
{
g_uc_role = MASTER_MODE;
puts("-I- Initialize SPI as master\r");
/* Configure an SPI peripheral. */
spi_enable_clock(SPI_MASTER_BASE);
spi_disable(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_lastxfer(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS);
spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL,
SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL,
(sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS,
SPI_DLYBCT);
spi_enable(SPI_MASTER_BASE);
}
int cph_deca_spi_read(uint16_t headerLength, const uint8_t *headerBuffer, uint32_t readlength, uint8_t *readBuffer) {
status_code_t result = STATUS_OK;
uint8_t pcs = DW_CHIP_SELECT;
uint16_t data;
for(int i = 0; i < headerLength; i++)
{
spi_write(DW_SPI, headerBuffer[i], 0, 0);
spi_read(DW_SPI, &data, &pcs);
}
for(int i = 0; i < readlength; i++)
{
if (i == (readlength - 1))
spi_set_lastxfer(DW_SPI);
spi_write(DW_SPI, 0xFF, 0, 0);
spi_read(DW_SPI, &data, &pcs);
readBuffer[i] = data & 0xFF;
}
while (spi_is_tx_empty(DW_SPI) == 0) ;
return result;
}
OSStatus host_platform_bus_init( void )
{
#ifndef USE_OWN_SPI_DRV
struct spi_master_vec_config spi;
#else
pdc_packet_t pdc_spi_packet;
#endif
OSStatus result;
MCU_CLOCKS_NEEDED();
spi_disable_interrupt(SPI_MASTER_BASE, 0xffffffff);
//Disable_global_interrupt();//TBD!
result = mico_rtos_init_semaphore( &spi_transfer_finished_semaphore, 1 );
if ( result != kNoErr )
{
return result;
}
mico_gpio_initialize( (mico_gpio_t)MICO_GPIO_9, INPUT_PULL_UP );
//ioport_port_mask_t ul_mask = ioport_pin_to_mask(CREATE_IOPORT_PIN(PORTA,24));
//pio_set_input(PIOA,ul_mask, PIO_PULLUP|PIO_DEBOUNCE);
mico_gpio_enable_IRQ( (mico_gpio_t)MICO_GPIO_9, IRQ_TRIGGER_RISING_EDGE, spi_irq_handler, NULL );
#ifndef HARD_CS_NSS0
mico_gpio_initialize( MICO_GPIO_15, OUTPUT_PUSH_PULL);//spi ss/cs
mico_gpio_output_high( MICO_GPIO_15 );//MICO_GPIO_15 TBD!
#else
ioport_set_pin_peripheral_mode(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS);//TBD!
#endif
/* set PORTB 01 to high to put WLAN module into g_SPI mode */
mico_gpio_initialize( (mico_gpio_t)WL_GPIO0, OUTPUT_PUSH_PULL );
mico_gpio_output_high( (mico_gpio_t)WL_GPIO0 );
#ifdef USE_OWN_SPI_DRV
#if (SAMG55)
/* Enable the peripheral and set SPI mode. */
flexcom_enable(BOARD_FLEXCOM_SPI);
flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
#else
/* Configure an SPI peripheral. */
pmc_enable_periph_clk(SPI_ID);
#endif
//Init pdc, and clear RX TX.
spi_m_pdc = spi_get_pdc_base(SPI_MASTER_BASE);
pdc_spi_packet.ul_addr = NULL;
pdc_spi_packet.ul_size = 3;
pdc_tx_init(spi_m_pdc, &pdc_spi_packet, NULL);
pdc_rx_init(spi_m_pdc, &pdc_spi_packet, NULL);
spi_disable(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_lastxfer(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
#ifdef HARD_CS_NSS0
//spi_enable_peripheral_select_decode(SPI_MASTER_BASE);
//spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_SEL);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS); //use soft nss comment here
#endif
spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / SPI_BAUD_RATE));
spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
/* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */
/* otherwise FreeRTOS will not be able to mask the interrupt */
/* keep in mind that ARMCM3 interrupt priority logic is inverted, the highest value */
/* is the lowest priority */
/* Configure SPI interrupts . */
spi_enable_interrupt(SPI_MASTER_BASE, SPI_IER_RXBUFF);
//spi_enable_interrupt(SPI_MASTER_BASE, SPI_IER_NSSR | SPI_IER_RXBUFF);
NVIC_DisableIRQ(SPI_IRQn);
//irq_register_handler(SPI_IRQn, 3);
NVIC_ClearPendingIRQ(SPI_IRQn);
NVIC_SetPriority(SPI_IRQn, 3);
NVIC_EnableIRQ(SPI_IRQn);
spi_enable(SPI_MASTER_BASE);
#else
spi.baudrate = SPI_BAUD_RATE;
if (STATUS_OK != spi_master_vec_init(&spi_master, SPI_MASTER_BASE, &spi)) {
return -1;
}
spi_master_vec_enable(&spi_master);
#endif
//if (!Is_global_interrupt_enabled())
// Enable_global_interrupt();
MCU_CLOCKS_NOT_NEEDED();
return kNoErr;
}
/**
* \brief Test SPI transfer.
*
* This test tests SPI read/write.
*
* \param test Current test case.
*/
static void run_spi_trans_test(const struct test_case *test)
{
spi_status_t rc;
uint16_t spi_data;
uint8_t spi_pcs;
spi_reset(CONF_TEST_SPI);
spi_set_lastxfer(CONF_TEST_SPI);
spi_set_master_mode(CONF_TEST_SPI);
spi_disable_mode_fault_detect(CONF_TEST_SPI);
spi_set_peripheral_chip_select_value(CONF_TEST_SPI, CONF_TEST_SPI_NPCS);
spi_set_clock_polarity(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS, SPI_CLK_POLARITY);
spi_set_clock_phase(CONF_TEST_SPI, CONF_TEST_SPI_NPCS, SPI_CLK_PHASE);
spi_set_bits_per_transfer(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS,
(sysclk_get_cpu_hz() / TEST_CLOCK));
spi_set_transfer_delay(CONF_TEST_SPI,
CONF_TEST_SPI_NPCS, SPI_DLYBS, SPI_DLYBCT);
spi_set_variable_peripheral_select(CONF_TEST_SPI);
spi_enable_loopback(CONF_TEST_SPI);
/* Test read/write timeout: should return SPI_ERROR_TIMEOUT. */
rc = spi_write(CONF_TEST_SPI, TEST_PATTERN, TEST_PCS, 1);
test_assert_true(test, rc == SPI_ERROR_TIMEOUT,
"Test SPI Write timeout: return code should not be %d", rc);
rc = spi_read(CONF_TEST_SPI, &spi_data, &spi_pcs);
test_assert_true(test, rc == SPI_ERROR_TIMEOUT,
"Test SPI Read timeout: return code should not be %d", rc);
spi_enable(CONF_TEST_SPI);
spi_enable_interrupt(CONF_TEST_SPI, SPI_IER_TDRE|SPI_IER_RDRF);
NVIC_EnableIRQ((IRQn_Type)CONF_TEST_SPI_ID);
/* Test write: should return OK. */
rc = spi_write(CONF_TEST_SPI, TEST_PATTERN, TEST_PCS, 1);
test_assert_true(test, rc == SPI_OK,
"Test SPI Write: return code should not be %d", rc);
/* Test read: should return OK with what is sent. */
rc = spi_read(CONF_TEST_SPI, &spi_data, &spi_pcs);
test_assert_true(test, rc == SPI_OK,
"Test SPI Read: return code should not be %d", rc);
test_assert_true(test, spi_data == TEST_PATTERN,
"Unexpected SPI data: %x, should be %x",
spi_data, TEST_PATTERN);
test_assert_true(test, spi_pcs == TEST_PCS,
"Unexpected SPI PCS: %x, should be %x",
spi_pcs, TEST_PCS);
/* Check interrupts. */
test_assert_true(test, g_b_spi_interrupt_tx_ready,
"Test SPI TX interrupt not detected");
test_assert_true(test, g_b_spi_interrupt_rx_ready,
"Test SPI RX interrupt not detected");
/* Done, disable SPI and all interrupts. */
spi_disable_loopback(CONF_TEST_SPI);
spi_disable(CONF_TEST_SPI);
spi_disable_interrupt(CONF_TEST_SPI, 0xFFFFFFFF);
NVIC_DisableIRQ((IRQn_Type)CONF_TEST_SPI_ID);
}
/*
* Configure the SPI hardware, including SPI clock speed, mode, delays, chip select pins
* It uses values listed in
*/
void AJ_WSL_SPI_InitializeSPIController(void)
{
uint32_t config;
/* Initialize and enable DMA controller. */
pmc_enable_periph_clk(ID_DMAC);
dmac_init(DMAC);
dmac_set_priority_mode(DMAC, DMAC_PRIORITY_ROUND_ROBIN);
dmac_enable(DMAC);
/* Configure DMA TX channel. */
config = 0;
config |= DMAC_CFG_DST_PER(AJ_SPI_TX_INDEX) |
DMAC_CFG_DST_H2SEL |
DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
dmac_channel_set_configuration(DMAC, AJ_DMA_TX_CHANNEL, config);
/* Configure DMA RX channel. */
config = 0;
config |= DMAC_CFG_SRC_PER(AJ_SPI_RX_INDEX) |
DMAC_CFG_SRC_H2SEL |
DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
dmac_channel_set_configuration(DMAC, AJ_DMA_RX_CHANNEL, config);
/* Enable receive channel interrupt for DMAC. */
uint8_t* interruptEnableAddress = AJ_SPI_ISER1_IEN_ADDR;
*interruptEnableAddress = AJ_SPI_DMAC_IEN_BIT;
dmac_enable_interrupt(DMAC, (1 << AJ_DMA_RX_CHANNEL));
dmac_enable_interrupt(DMAC, (1 << AJ_DMA_TX_CHANNEL));
//AJ_WSL_DMA_Setup();
dmac_channel_disable(DMAC, AJ_DMA_TX_CHANNEL);
dmac_channel_disable(DMAC, AJ_DMA_RX_CHANNEL);
/*
* Configure the hardware to enable SPI and some output pins
*/
{
pmc_enable_periph_clk(ID_PIOA);
pmc_enable_periph_clk(ID_PIOB);
pmc_enable_periph_clk(ID_PIOC);
pmc_enable_periph_clk(ID_PIOD);
// make all of these pins controlled by the right I/O controller
pio_configure_pin_group(PIOA, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_A);
pio_configure_pin_group(PIOB, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_B);
pio_configure_pin_group(PIOC, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_C);
pio_configure_pin_group(PIOD, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_D);
/*
* Reset the device by toggling the CHIP_POWER
*/
ioport_set_pin_dir(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_PIN_LEVEL_LOW);
AJ_Sleep(10);
ioport_set_pin_level(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_PIN_LEVEL_HIGH);
/*
* Reset the device by toggling the CHIP_PWD# signal
*/
ioport_set_pin_dir(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_PIN_LEVEL_LOW);
AJ_Sleep(10);
ioport_set_pin_level(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_PIN_LEVEL_HIGH);
/* configure the pin that detects SPI data ready from the target chip */
ioport_set_pin_dir(AJ_WSL_SPI_CHIP_SPI_INT_PIN, IOPORT_DIR_INPUT);
ioport_set_pin_sense_mode(AJ_WSL_SPI_CHIP_SPI_INT_PIN, IOPORT_SENSE_LEVEL_LOW);
pio_handler_set(PIOC, ID_PIOC, AJ_WSL_SPI_CHIP_SPI_INT_BIT, (PIO_PULLUP | PIO_IT_FALL_EDGE), &AJ_WSL_SPI_CHIP_SPI_ISR);
pio_handler_set_priority(PIOD, (IRQn_Type) ID_PIOC, 0xB);
pio_enable_interrupt(PIOC, AJ_WSL_SPI_CHIP_SPI_INT_BIT);
}
spi_enable_clock(AJ_WSL_SPI_DEVICE);
spi_reset(AJ_WSL_SPI_DEVICE);
spi_set_lastxfer(AJ_WSL_SPI_DEVICE);
spi_set_master_mode(AJ_WSL_SPI_DEVICE);
spi_disable_mode_fault_detect(AJ_WSL_SPI_DEVICE);
spi_set_peripheral_chip_select_value(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS);
spi_set_clock_polarity(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_CLOCK_POLARITY);
spi_set_clock_phase(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_CLOCK_PHASE);
spi_set_bits_per_transfer(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, (sysclk_get_cpu_hz() / AJ_WSL_SPI_CLOCK_RATE));
spi_set_transfer_delay(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_DELAY_BEFORE_CLOCK, AJ_WSL_SPI_DELAY_BETWEEN_TRANSFERS);
spi_set_fixed_peripheral_select(AJ_WSL_SPI_DEVICE);
spi_configure_cs_behavior(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, SPI_CS_RISE_FORCED);
spi_enable_interrupt(AJ_WSL_SPI_DEVICE, SPI_IER_TDRE | SPI_IER_RDRF);
spi_enable(AJ_WSL_SPI_DEVICE);
}
// Here should be all the initialization functions for the module before 12v power
void init_module_peripherals_bp(void)
{
/* LEDs IO */
pmc_enable_periph_clk(IN_CLK_LED1_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_CLK_LED2_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_CLK_LED3_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED1_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED2_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED3_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED1_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED2_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED3_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED1_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED2_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED3_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
/* Pulse inputs/state & d reset output */
pmc_enable_periph_clk(OUT_PULSE_DET_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(DATA_IN_DET_PIO_ID);
ioport_set_pin_dir(DATA_IN_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(CLK_IN_DET_PIO_ID);
ioport_set_pin_dir(CLK_IN_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(OUT_PULSE_STATE_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(DATA_IN_STATE_PIO_ID);
ioport_set_pin_dir(DATA_IN_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(CLK_IN_STATE_PIO_ID);
ioport_set_pin_dir(CLK_IN_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(OUT_PULSE_RST_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(DATA_PULSE_RST_PIO_ID);
ioport_set_pin_dir(DATA_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(CLK_PULSE_RST_PIO_ID);
ioport_set_pin_dir(CLK_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLK_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
/* Sload */
pmc_enable_periph_clk(DATA_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(DATA_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(CLOCK_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(CLOCK_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLOCK_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(RESET_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(RESET_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RESET_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(RF_ATTEN_SLOAD_PIO_ID);
ioport_set_pin_dir(RF_ATTEN_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RF_ATTEN_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
/* Delay enables */
pmc_enable_periph_clk(DATA_DELAY_EN_PIO_ID);
ioport_set_pin_dir(DATA_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
pmc_enable_periph_clk(CLOCK_DELAY_EN_PIO_ID);
ioport_set_pin_dir(CLOCK_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLOCK_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
pmc_enable_periph_clk(RESET_DELAY_EN_PIO_ID);
ioport_set_pin_dir(RESET_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RESET_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
// Init LED interrupt,
uint32_t ul_div;
uint32_t ul_tcclks;
/* Get system clock. */
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Configure PMC. */
pmc_enable_periph_clk(ID_TC1);
/* Configure TC for a TC_FREQ frequency and trigger on RC compare. */
tc_find_mck_divisor(20, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 1, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 1, (ul_sysclk / ul_div) / 20);
/* Configure and enable interrupt on RC compare. */
tc_start(TC0, 1);
NVIC_DisableIRQ(TC1_IRQn);
NVIC_ClearPendingIRQ(TC1_IRQn);
//NVIC_SetPriority(TC1_IRQn, 0);
NVIC_EnableIRQ((IRQn_Type)ID_TC1);
tc_enable_interrupt(TC0, 1, TC_IER_CPCS);
/* SPI interface */
gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS);
gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS);
gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS);
//gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); // Controled by software
/* Configure an SPI peripheral. */
spi_enable_clock(SPI0);
spi_disable(SPI0);
spi_reset(SPI0);
spi_set_lastxfer(SPI0);
spi_set_master_mode(SPI0);
spi_disable_mode_fault_detect(SPI0);
/* Set variable chip select */
spi_set_variable_peripheral_select(SPI0);
/* Configure delay SPI channel */
spi_set_clock_polarity(SPI0, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI0, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI0, SPI_CHIP_SEL, SPI_CSR_BITS_11_BIT);
spi_configure_cs_behavior(SPI0, SPI_CHIP_SEL, SPI_CS_RISE_FORCED);
spi_set_baudrate_div(SPI0, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI0, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
/* Configure RF atten SPI channel */
spi_set_clock_polarity(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI0, SPI_ALT_CHIP_SEL, SPI_CSR_BITS_16_BIT);
spi_configure_cs_behavior(SPI0, SPI_ALT_CHIP_SEL, SPI_CS_RISE_FORCED);
spi_set_baudrate_div(SPI0, SPI_ALT_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI0, SPI_ALT_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
/* Enable SPI */
spi_enable(SPI0);
}
OSStatus host_platform_bus_init( void )
{
pdc_packet_t pdc_spi_packet;
Pdc* spi_pdc = spi_get_pdc_base( wifi_spi.port );
platform_mcu_powersave_disable( );
mico_rtos_init_semaphore( &spi_transfer_finished_semaphore, 1 );
/* Setup the SPI lines */
platform_gpio_peripheral_pin_init( wifi_spi.mosi_pin, ( wifi_spi.mosi_pin_mux_mode | IOPORT_MODE_PULLUP ) );
platform_gpio_peripheral_pin_init( wifi_spi.miso_pin, ( wifi_spi.miso_pin_mux_mode | IOPORT_MODE_PULLUP ) );
platform_gpio_peripheral_pin_init( wifi_spi.clock_pin, ( wifi_spi.clock_pin_mux_mode | IOPORT_MODE_PULLUP ) );
/* Setup the interrupt input for WLAN_IRQ */
platform_gpio_init( &wifi_spi_pins[WIFI_PIN_SPI_IRQ], INPUT_HIGH_IMPEDANCE );
platform_gpio_irq_enable( &wifi_spi_pins[WIFI_PIN_SPI_IRQ], IRQ_TRIGGER_RISING_EDGE, spi_irq_handler, 0 );
/* Setup SPI slave select GPIOs */
platform_gpio_init( &wifi_spi_pins[WIFI_PIN_SPI_CS], OUTPUT_PUSH_PULL );
platform_gpio_output_high( &wifi_spi_pins[WIFI_PIN_SPI_CS] );
#if defined ( MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP )
/* Set GPIO_B[1:0] to 01 to put WLAN module into gSPI mode */
platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0], OUTPUT_PUSH_PULL );
platform_gpio_output_high( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0] );
platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1], OUTPUT_PUSH_PULL );
platform_gpio_output_low( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1] );
#endif
/* Enable the peripheral and set SPI mode. */
flexcom_enable( flexcom_base[ wifi_spi.spi_id ] );
flexcom_set_opmode( flexcom_base[ wifi_spi.spi_id ], FLEXCOM_SPI );
/* Init pdc, and clear RX TX. */
pdc_spi_packet.ul_addr = 0;
pdc_spi_packet.ul_size = 1;
pdc_tx_init( spi_pdc, &pdc_spi_packet, NULL );
pdc_rx_init( spi_pdc, &pdc_spi_packet, NULL );
spi_disable_interrupt(wifi_spi.port, 0xffffffff );
spi_disable( wifi_spi.port );
spi_reset( wifi_spi.port );
spi_set_lastxfer( wifi_spi.port );
spi_set_master_mode( wifi_spi.port );
spi_disable_mode_fault_detect( wifi_spi.port );
spi_set_clock_polarity( wifi_spi.port, 0, SPI_CLK_POLARITY );
spi_set_clock_phase( wifi_spi.port, 0, SPI_CLK_PHASE );
spi_set_bits_per_transfer( wifi_spi.port, 0, SPI_CSR_BITS_8_BIT );
spi_set_baudrate_div( wifi_spi.port, 0, (sysclk_get_cpu_hz() / SPI_BAUD_RATE) );
spi_set_transfer_delay( wifi_spi.port, 0, 0, 0 );
/* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */
/* otherwise FreeRTOS will not be able to mask the interrupt */
/* keep in mind that ARMCM4 interrupt priority logic is inverted, the highest value */
/* is the lowest priority */
/* Configure SPI interrupts . */
NVIC_EnableIRQ( platform_flexcom_irq_numbers[wifi_spi.spi_id] );
spi_enable(wifi_spi.port);
platform_mcu_powersave_enable( );
return kNoErr;
}
