static void go_to_mcidle(int cpu)
{
if(spm_mcdi_wfi(cpu)==1)
mcidle_cnt[cpu]+=1;
if(g_SPM_MCDI_Abnormal_WakeUp!=g_pre_SPM_MCDI_Abnormal_WakeUp)
{
printk("SPM-MCDI Abnormal %x\n",g_SPM_MCDI_Abnormal_WakeUp);
g_pre_SPM_MCDI_Abnormal_WakeUp = g_SPM_MCDI_Abnormal_WakeUp;
}
}
static bool go_to_mcidle(int cpu)
{
bool ret = 0;
ret = spm_mcdi_wfi(cpu);
if(g_SPM_MCDI_Abnormal_WakeUp!=g_pre_SPM_MCDI_Abnormal_WakeUp)
{
printk("SPM-MCDI Abnormal %x\n",g_SPM_MCDI_Abnormal_WakeUp);
g_pre_SPM_MCDI_Abnormal_WakeUp = g_SPM_MCDI_Abnormal_WakeUp;
}
return ret;
}
int spm_wfi_for_sodi_test(void *sodi_data)
{
volatile u32 do_not_change_it;
volatile u32 lo, hi, core_id;
unsigned long flags;
//u32 temp_address;
preempt_disable();
do_not_change_it = 1;
MCDI_Test_Mode = 1;
while(do_not_change_it)
{
/* Mask ARM i bit */
local_irq_save(flags);
core_id = (u32)smp_processor_id();
// set local timer & GPT =========================================
switch (core_id)
{
case 0 :
read_cntp_cval(lo, hi);
hi+=0xffffffff; // very very long
write_cntp_cval(lo, hi);
write_cntp_ctl(0x1); // CNTP_CTL_ENABLE
break;
case 1 :
stop_gpt(GPT4); // disable GPT
break;
default : break;
}
spm_mcdi_wfi();
/* Un-Mask ARM i bit */
local_irq_restore(flags);
}
preempt_enable();
return 0;
}
int spm_wfi_for_mcdi_test(void *mcdi_data)
{
volatile u32 do_not_change_it;
volatile u32 lo, hi, core_id;
unsigned long flags;
preempt_disable();
do_not_change_it = 1;
MCDI_Test_Mode = 1;
while(do_not_change_it)
{
/* Mask ARM i bit */
local_irq_save(flags);
core_id = (u32)smp_processor_id();
// set local timer & GPT =========================================
switch (core_id)
{
case 0 :
#if 0
/*trigger pcm timer*/
spm_write(SPM_POWER_ON_VAL1,(spm_read(SPM_POWER_ON_VAL1)&0xFFFFFFCF)|0x220);
spm_write(SPM_PCM_PWR_IO_EN,0x00800000);
spm_write(SPM_PCM_PWR_IO_EN,0x00000000);
#else
read_cntp_cval(lo, hi);
lo+=26000; // 100 ms, 13MHz
//lo+=5070000; // 390 ms, 13MHz
write_cntp_cval(lo, hi);
write_cntp_ctl(0x1); // CNTP_CTL_ENABLE
//printk("mcdi pdn cnt:%d\n",cpu_power_down_cnt);
#endif
break;
case 1 :
#if 0
//gpt_set_cmp(GPT4, 2470000); // 190ms, 13MHz
//printk("mcdi pdn cnt:%d\n",cpu_power_down_cnt);
gpt_set_cmp(GPT4, 130000); // 10ms, 13MHz
start_gpt(GPT4);
#endif
read_cntp_cval(lo, hi);
lo+=26000; // 100 ms, 13MHz
//lo+=5070000; // 390 ms, 13MHz
write_cntp_cval(lo, hi);
write_cntp_ctl(0x1); // CNTP_CTL_ENABLE
spm_mcdi_before_wfi(core_id);
break;
default : break;
}
spm_mcdi_wfi();
if(core_id==1)
spm_mcdi_after_wfi(core_id);
/* Un-Mask ARM i bit */
local_irq_restore(flags);
}
preempt_enable();
return 0;
}
