int spm_mtcmos_ctrl_mdsys1(int state)
{
int err = 0;
volatile unsigned int val;
unsigned long flags;
int count = 0;
spm_mtcmos_noncpu_lock(flags);
if (state == STA_POWER_DOWN) {
spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | MD1_PROT_MASK);
while ((spm_read(TOPAXI_PROT_STA1) & MD1_PROT_MASK) != MD1_PROT_MASK) {
count++;
if(count>1000)
break;
}
spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) | MD_SRAM_PDN);
spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) | PWR_ISO);
val = spm_read(SPM_MD_PWR_CON);
val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
spm_write(SPM_MD_PWR_CON, val);
spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) & ~(PWR_ON | PWR_ON_2ND));
while ((spm_read(SPM_PWR_STATUS) & MD1_PWR_STA_MASK)
|| (spm_read(SPM_PWR_STATUS_2ND) & MD1_PWR_STA_MASK)) {
}
//#ifdef MTK_LTE_SUPPORT
// spm_write(AP_PLL_CON7, (spm_read(AP_PLL_CON7) | 0xF)); //force off LTE
//#endif
} else { /* STA_POWER_ON */
//#ifdef MTK_LTE_SUPPORT
// spm_write(AP_PLL_CON7, (spm_read(AP_PLL_CON7) & (~0xF))); //turn on LTE
//#endif
spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) | PWR_ON);
spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) | PWR_ON_2ND);
while (!(spm_read(SPM_PWR_STATUS) & MD1_PWR_STA_MASK)
|| !(spm_read(SPM_PWR_STATUS_2ND) & MD1_PWR_STA_MASK)) {
}
spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) & ~PWR_CLK_DIS);
spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) & ~PWR_ISO);
spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) | PWR_RST_B);
spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) & ~MD_SRAM_PDN);
spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~MD1_PROT_MASK);
while (spm_read(TOPAXI_PROT_STA1) & MD1_PROT_MASK) {
}
}
spm_mtcmos_noncpu_unlock(flags);
return err;
}
int spm_mtcmos_ctrl_mfg(int state)
{
int err = 0;
volatile unsigned int val;
unsigned long flags;
spm_mtcmos_noncpu_lock(flags);
if (state == STA_POWER_DOWN) {
spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | MFG_2D_PROT_MASK);
while ((spm_read(TOPAXI_PROT_STA1) & MFG_2D_PROT_MASK) != MFG_2D_PROT_MASK) {
}
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | MFG_SRAM_PDN);
while ((spm_read(SPM_MFG_PWR_CON) & MFG_SRAM_ACK) != MFG_SRAM_ACK) {
}
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ISO);
val = spm_read(SPM_MFG_PWR_CON);
val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
spm_write(SPM_MFG_PWR_CON, val);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~(PWR_ON | PWR_ON_2ND));
while ((spm_read(SPM_PWR_STATUS) & MFG_PWR_STA_MASK)
|| (spm_read(SPM_PWR_STATUS_2ND) & MFG_PWR_STA_MASK)) {
}
} else { /* STA_POWER_ON */
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ON);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ON_2ND);
while (!(spm_read(SPM_PWR_STATUS) & MFG_PWR_STA_MASK) ||
!(spm_read(SPM_PWR_STATUS_2ND) & MFG_PWR_STA_MASK)) {
}
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~PWR_CLK_DIS);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~PWR_ISO);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_RST_B);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~MFG_SRAM_PDN);
while ((spm_read(SPM_MFG_PWR_CON) & MFG_SRAM_ACK)) {
}
spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~MFG_2D_PROT_MASK);
while (spm_read(TOPAXI_PROT_STA1) & MFG_2D_PROT_MASK) {
}
}
spm_mtcmos_noncpu_unlock(flags);
return err;
}
/**
*test_spm_gpu_power_on - test whether gpu could be powered on
*
*Returns 1 if power on operation succeed, 0 otherwise.
*/
int test_spm_gpu_power_on(void)
{
int i;
volatile unsigned int sta1, sta2;
volatile unsigned int val;
unsigned long flags;
sta1 = spm_read(SPM_PWR_STATUS);
sta2 = spm_read(SPM_PWR_STATUS_S);
if (((sta1 & MFG_PWR_STA_MASK) == MFG_PWR_STA_MASK) &&
((sta2 & MFG_PWR_STA_MASK) == MFG_PWR_STA_MASK)) {
printk("[%s]: test_spm_gpu_power_on already on, return: 1.\n", __func__);
return 1;
}
spm_mtcmos_noncpu_lock(flags);
val = spm_read(SPM_MFG_PWR_CON);
BUG_ON(!(val & PWR_ISO));
for(i = 0; i < 5; i++) {
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ON);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ON_S);
udelay(5);
sta1 = spm_read(SPM_PWR_STATUS);
sta2 = spm_read(SPM_PWR_STATUS_S);
if (((sta1 & MFG_PWR_STA_MASK) != MFG_PWR_STA_MASK) ||
((sta2 & MFG_PWR_STA_MASK) != MFG_PWR_STA_MASK)) {
spm_mtcmos_noncpu_unlock(flags);
printk("[%s]: test_spm_gpu_power_on return: 0.\n", __func__);
return 0;
}
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~(PWR_ON | PWR_ON_S));
sta1 = spm_read(SPM_PWR_STATUS);
sta2 = spm_read(SPM_PWR_STATUS_S);
if (((sta1 & MFG_PWR_STA_MASK) == MFG_PWR_STA_MASK) ||
((sta2 & MFG_PWR_STA_MASK) == MFG_PWR_STA_MASK)) {
spm_mtcmos_noncpu_unlock(flags);
printk("[%s]: test_spm_gpu_power_on return: 0.\n", __func__);
return 0;
}
mdelay(1);
}
spm_mtcmos_noncpu_unlock(flags);
printk("[%s]: test_spm_gpu_power_on return: 1.\n", __func__);
return 1;
}
int spm_mtcmos_ctrl_ddrphy(int state)
{
int err = 0;
volatile unsigned int val;
unsigned long flags;
spm_mtcmos_noncpu_lock(flags);
if (state == STA_POWER_DOWN) {
spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) | PWR_ISO);
val = spm_read(SPM_DPY_PWR_CON);
val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
spm_write(SPM_DPY_PWR_CON, val);
spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) & ~(PWR_ON | PWR_ON_S));
#if 0
udelay(1);
if (spm_read(SPM_PWR_STATUS) & DPY_PWR_STA_MASK) {
err = 1;
}
#else
while ((spm_read(SPM_PWR_STATUS) & DPY_PWR_STA_MASK)
|| (spm_read(SPM_PWR_STATUS_S) & DPY_PWR_STA_MASK)) {
}
#endif
} else { /* STA_POWER_ON */
spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) | PWR_ON);
spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) | PWR_ON_S);
#if 0
udelay(1);
#else
while (!(spm_read(SPM_PWR_STATUS) & DPY_PWR_STA_MASK)
|| !(spm_read(SPM_PWR_STATUS_S) & DPY_PWR_STA_MASK)) {
}
#endif
spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) & ~PWR_CLK_DIS);
spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) & ~PWR_ISO);
spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) | PWR_RST_B);
#if 0
udelay(1);
if (!(spm_read(SPM_PWR_STATUS) & DPY_PWR_STA_MASK)) {
err = 1;
}
#endif
}
spm_mtcmos_noncpu_unlock(flags);
return err;
}
int spm_topaxi_prot(int bit, int en)
{
unsigned long flags;
spm_mtcmos_noncpu_lock(flags);
if (en == 1) {
spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | (1<<bit));
while ((spm_read(TOPAXI_PROT_STA1) & (1<<bit)) != (1<<bit)) {
}
} else {
spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~(1<<bit));
while (spm_read(TOPAXI_PROT_STA1) & (1<<bit)) {
}
}
spm_mtcmos_noncpu_unlock(flags);
return 0;
}
int spm_ctrl_e3tcm(int state)
{
int err = 0;
unsigned long flags;
spm_mtcmos_noncpu_lock(flags);
if (state == STA_POWER_DOWN) {
spm_write(SPM_PCM_PASR_DPD_2, spm_read(SPM_PCM_PASR_DPD_2) | (1<<14));
spm_write(SPM_PCM_PASR_DPD_2, spm_read(SPM_PCM_PASR_DPD_2) & ~(1<<15));
spm_write(SPM_PCM_PASR_DPD_2, spm_read(SPM_PCM_PASR_DPD_2) | E3TCM_SRAM_PDN);
while ((spm_read(SPM_PCM_PASR_DPD_2) & E3TCM_SRAM_ACK) !=E3TCM_SRAM_ACK) {
}
} else { /* STA_POWER_ON */
spm_write(SPM_PCM_PASR_DPD_2, spm_read(SPM_PCM_PASR_DPD_2) & ~E3TCM_SRAM_PDN);
while ((spm_read(SPM_PCM_PASR_DPD_2) & E3TCM_SRAM_ACK)) {
}
spm_write(SPM_PCM_PASR_DPD_2, spm_read(SPM_PCM_PASR_DPD_2) | (1<<15));
spm_write(SPM_PCM_PASR_DPD_2, spm_read(SPM_PCM_PASR_DPD_2) & ~(1<<14));
}
spm_mtcmos_noncpu_unlock(flags);
return err;
}
int spm_mtcmos_ctrl_vdec(int state)
{
int err = 0;
volatile unsigned int val;
unsigned long flags;
int count = 0;
spm_mtcmos_noncpu_lock(flags);
if (state == STA_POWER_DOWN) {
spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) | SRAM_PDN);
while ((spm_read(SPM_VDE_PWR_CON) & VDE_SRAM_ACK) != VDE_SRAM_ACK) {
count++;
if (count > 1000 && count<1010) {
printk("there is no fmm_clk, CLK_CFG_0 = 0x%x\n", spm_read(CLK_CFG_0));
}
if (count > 2000) {
clk_stat_check(SYS_DIS);
BUG();
}
}
spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) | PWR_ISO);
val = spm_read(SPM_VDE_PWR_CON);
val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
spm_write(SPM_VDE_PWR_CON, val);
spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) & ~(PWR_ON | PWR_ON_2ND));
while ((spm_read(SPM_PWR_STATUS) & VDE_PWR_STA_MASK)
|| (spm_read(SPM_PWR_STATUS_2ND) & VDE_PWR_STA_MASK)) {
}
} else { /* STA_POWER_ON */
spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) | PWR_ON);
spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) | PWR_ON_2ND);
while (!(spm_read(SPM_PWR_STATUS) & VDE_PWR_STA_MASK)
|| !(spm_read(SPM_PWR_STATUS_2ND) & VDE_PWR_STA_MASK)) {
}
spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) & ~PWR_CLK_DIS);
spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) & ~PWR_ISO);
spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) | PWR_RST_B);
spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) & ~SRAM_PDN);
while ((spm_read(SPM_VDE_PWR_CON) & VDE_SRAM_ACK)) {
count++;
if (count > 1000 && count<1010) {
printk("there is no fmm_clk, CLK_CFG_0 = 0x%x\n", spm_read(CLK_CFG_0));
}
if (count > 2000) {
clk_stat_check(SYS_DIS);
BUG();
}
}
}
spm_mtcmos_noncpu_unlock(flags);
return err;
}
int spm_mtcmos_ctrl_disp(int state)
{
int err = 0;
volatile unsigned int val;
unsigned long flags;
spm_mtcmos_noncpu_lock(flags);
if (state == STA_POWER_DOWN) {
spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | DISP_PROT_MASK);
while ((spm_read(TOPAXI_PROT_STA1) & DISP_PROT_MASK) != DISP_PROT_MASK) {
}
spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | SRAM_PDN);
#if 0
while ((spm_read(SPM_DIS_PWR_CON) & DIS_SRAM_ACK) != DIS_SRAM_ACK) {
}
#endif
spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ISO);
val = spm_read(SPM_DIS_PWR_CON);
//val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
val = val | PWR_CLK_DIS;
spm_write(SPM_DIS_PWR_CON, val);
//spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~(PWR_ON | PWR_ON_2ND));
#if 0
udelay(1);
if (spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK) {
err = 1;
}
#else
//while ((spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)
// || (spm_read(SPM_PWR_STATUS_S) & DIS_PWR_STA_MASK)) {
//}
#endif
} else { /* STA_POWER_ON */
//spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ON);
//spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ON_2ND);
#if 0
udelay(1);
#else
//while (!(spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)
// || !(spm_read(SPM_PWR_STATUS_S) & DIS_PWR_STA_MASK)) {
//}
#endif
spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~PWR_CLK_DIS);
spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~PWR_ISO);
//spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_RST_B);
spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~SRAM_PDN);
#if 0
while ((spm_read(SPM_DIS_PWR_CON) & DIS_SRAM_ACK)) {
}
#endif
#if 0
udelay(1);
if (!(spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)) {
err = 1;
}
#endif
spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~DISP_PROT_MASK);
while (spm_read(TOPAXI_PROT_STA1) & DISP_PROT_MASK) {
}
}
spm_mtcmos_noncpu_unlock(flags);
return err;
}
int spm_mtcmos_ctrl_connsys(int state)
{
int err = 0;
volatile unsigned int val;
unsigned long flags;
int count = 0;
spm_mtcmos_noncpu_lock(flags);
if (state == STA_POWER_DOWN) {
spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | CONN_PROT_MASK);
while ((spm_read(TOPAXI_PROT_STA1) & CONN_PROT_MASK) != CONN_PROT_MASK) {
count++;
if(count>1000)
break;
}
spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) | MD_SRAM_PDN);
spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) | PWR_ISO);
val = spm_read(SPM_CONN_PWR_CON);
val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
spm_write(SPM_CONN_PWR_CON, val);
spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) & ~(PWR_ON | PWR_ON_S));
#if 0
udelay(1);
if (spm_read(SPM_PWR_STATUS) & CONN_PWR_STA_MASK) {
err = 1;
}
#else
while ((spm_read(SPM_PWR_STATUS) & CONN_PWR_STA_MASK)
|| (spm_read(SPM_PWR_STATUS_S) & CONN_PWR_STA_MASK)) {
}
#endif
} else {
spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) | PWR_ON);
spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) | PWR_ON_S);
#if 0
udelay(1);
#else
while (!(spm_read(SPM_PWR_STATUS) & CONN_PWR_STA_MASK)
|| !(spm_read(SPM_PWR_STATUS_S) & CONN_PWR_STA_MASK)) {
}
#endif
spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) & ~PWR_CLK_DIS);
spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) & ~PWR_ISO);
spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) | PWR_RST_B);
spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) & ~MD_SRAM_PDN);
#if 0
udelay(1);
if (!(spm_read(SPM_PWR_STATUS) & CONN_PWR_STA_MASK)) {
err = 1;
}
#endif
spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~CONN_PROT_MASK);
while (spm_read(TOPAXI_PROT_STA1) & CONN_PROT_MASK) {
}
}
spm_mtcmos_noncpu_unlock(flags);
return err;
}
int spm_mtcmos_ctrl_mfg(int state)
{
int err = 0;
volatile unsigned int val;
unsigned long flags;
spm_mtcmos_noncpu_lock(flags);
if (state == STA_POWER_DOWN) {
// spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | MFG_PROT_MASK);
// while ((spm_read(TOPAXI_PROT_STA1) & MFG_PROT_MASK) != MFG_PROT_MASK) {
// }
// spm_write(TOPAXI_SI0_CTL, spm_read(TOPAXI_SI0_CTL) & ~MFG_SI0_MASK);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | SRAM_PDN);
while ((spm_read(SPM_MFG_PWR_CON) & MFG_SRAM_ACK) != MFG_SRAM_ACK) {
}
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ISO);
val = spm_read(SPM_MFG_PWR_CON);
val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
spm_write(SPM_MFG_PWR_CON, val);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~(PWR_ON | PWR_ON_S));
#if 0
udelay(1);
if (spm_read(SPM_PWR_STATUS) & MFG_PWR_STA_MASK) {
err = 1;
}
#else
while ((spm_read(SPM_PWR_STATUS) & MFG_PWR_STA_MASK)
|| (spm_read(SPM_PWR_STATUS_S) & MFG_PWR_STA_MASK)) {
}
#endif
} else { /* STA_POWER_ON */
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ON);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ON_S);
#if 0
udelay(1);
#else
while (!(spm_read(SPM_PWR_STATUS) & MFG_PWR_STA_MASK) ||
!(spm_read(SPM_PWR_STATUS_S) & MFG_PWR_STA_MASK)) {
}
#endif
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~PWR_CLK_DIS);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~PWR_ISO);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_RST_B);
spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~SRAM_PDN);
while ((spm_read(SPM_MFG_PWR_CON) & MFG_SRAM_ACK)) {
}
#if 0
udelay(1);
if (!(spm_read(SPM_PWR_STATUS) & MFG_PWR_STA_MASK)) {
err = 1;
}
#endif
// spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~MFG_PROT_MASK);
// while (spm_read(TOPAXI_PROT_STA1) & MFG_PROT_MASK) {
// }
// spm_write(TOPAXI_SI0_CTL, spm_read(TOPAXI_SI0_CTL) | MFG_SI0_MASK);
}
spm_mtcmos_noncpu_unlock(flags);
return err;
}
