void gpio_free(unsigned gpio) { switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) return; if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) return; clear_bit(gpio, gpio_in_use); return; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) return; clear_bit(gpio, gpio_in_use); return; #endif } }
int gpio_request(unsigned gpio, const char *tag) { switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) && ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) return -EINVAL; if (ssb_extif_available(&bcm47xx_bus.ssb.extif) && ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) return -EINVAL; if (test_and_set_bit(gpio, gpio_in_use)) return -EBUSY; return 0; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: if (gpio >= BCM47XX_CHIPCO_GPIO_LINES) return -EINVAL; if (test_and_set_bit(gpio, gpio_in_use)) return -EBUSY; return 0; #endif } return -EINVAL; }
int gpio_to_irq(unsigned gpio) { if (ssb_chipco_available(&ssb_bcm47xx.chipco)) return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2; else if (ssb_extif_available(&ssb_bcm47xx.extif)) return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2; else return -EINVAL; }
int ssb_gpio_init(struct ssb_bus *bus) { if (ssb_chipco_available(&bus->chipco)) return ssb_gpio_chipco_init(bus); else if (ssb_extif_available(&bus->extif)) return ssb_gpio_extif_init(bus); else SSB_WARN_ON(1); return -1; }
int ssb_gpio_unregister(struct ssb_bus *bus) { if (ssb_chipco_available(&bus->chipco) || ssb_extif_available(&bus->extif)) { gpiochip_remove(&bus->gpio); return 0; } else { SSB_WARN_ON(1); } return -1; }
void gpio_free(unsigned gpio) { if (ssb_chipco_available(&ssb_bcm47xx.chipco) && ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) return; if (ssb_extif_available(&ssb_bcm47xx.extif) && ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) return; clear_bit(gpio, gpio_in_use); }
u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value) { unsigned long flags; u32 res = 0; spin_lock_irqsave(&bus->gpio_lock, flags); if (ssb_chipco_available(&bus->chipco)) res = ssb_chipco_gpio_control(&bus->chipco, mask, value); spin_unlock_irqrestore(&bus->gpio_lock, flags); return res; }
int ssb_watchdog_timer_set(struct ssb_bus *bus, u32 ticks) { if (ssb_chipco_available(&bus->chipco)) { ssb_chipco_watchdog_timer_set(&bus->chipco, ticks); return 0; } if (ssb_extif_available(&bus->extif)) { ssb_extif_watchdog_timer_set(&bus->extif, ticks); return 0; } return -ENODEV; }
int gpio_request(unsigned gpio, const char *tag) { if (ssb_chipco_available(&ssb_bcm47xx.chipco) && ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES)) return -EINVAL; if (ssb_extif_available(&ssb_bcm47xx.extif) && ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES)) return -EINVAL; if (test_and_set_bit(gpio, gpio_in_use)) return -EBUSY; return 0; }
u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value) { unsigned long flags; u32 res = 0; spin_lock_irqsave(&bus->gpio_lock, flags); if (ssb_chipco_available(&bus->chipco)) res = ssb_chipco_gpio_outen(&bus->chipco, mask, value); else if (ssb_extif_available(&bus->extif)) res = ssb_extif_gpio_outen(&bus->extif, mask, value); else SSB_WARN_ON(1); spin_unlock_irqrestore(&bus->gpio_lock, flags); return res; }
int gpio_to_irq(unsigned gpio) { switch (bcm47xx_bus_type) { #ifdef CONFIG_BCM47XX_SSB case BCM47XX_BUS_TYPE_SSB: if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco)) return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2; else if (ssb_extif_available(&bcm47xx_bus.ssb.extif)) return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2; else return -EINVAL; #endif #ifdef CONFIG_BCM47XX_BCMA case BCM47XX_BUS_TYPE_BCMA: return bcma_core_mips_irq(bcm47xx_bus.bcma.bus.drv_cc.core) + 2; #endif } return -EINVAL; }