/**
* \brief Synchronous Serial Controller Handler.
*
*/
void SSC_Handler(void)
{
uint32_t ul_data;
ssc_get_status(SSC);
ssc_read(SSC, &ul_data);
g_uc_rx_buff[g_uc_rx_index++] = ul_data;
if (BUFFER_SIZE == g_uc_rx_index) {
g_uc_rx_done = 1;
ssc_disable_interrupt(SSC, SSC_IDR_RXRDY);
}
}
/**
* \brief Initial the ssc interface.
*/
static void init_ssc(void)
{
clock_opt_t tx_clk_option;
data_frame_opt_t tx_data_frame_option;
/* Initialize clock */
pmc_enable_periph_clk(ID_SSC);
/* Reset SSC */
ssc_reset(SSC);
/* Configure SSC */
ssc_set_clock_divider(SSC, SAMPLE_RATE * (BITS_BY_SLOT + 1) * 2,
sysclk_get_peripheral_hz());
/* Transmitter clock mode configuration. */
tx_clk_option.ul_cks = SSC_TCMR_CKS_MCK;
tx_clk_option.ul_cko = SSC_TCMR_CKO_CONTINUOUS;
tx_clk_option.ul_cki = 0;
tx_clk_option.ul_ckg = SSC_TCMR_CKG_NONE;
tx_clk_option.ul_start_sel = SSC_TCMR_START_RF_EDGE;
tx_clk_option.ul_sttdly = 1;
tx_clk_option.ul_period = BITS_BY_SLOT - 1;
/* Transmitter frame mode configuration. */
tx_data_frame_option.ul_datlen = BITS_BY_SLOT - 1;
tx_data_frame_option.ul_msbf = SSC_TFMR_MSBF;
tx_data_frame_option.ul_datnb = 0;
tx_data_frame_option.ul_fslen = BITS_BY_SLOT - 1;
tx_data_frame_option.ul_fslen_ext = 0;
tx_data_frame_option.ul_fsos = SSC_TFMR_FSOS_NEGATIVE;
tx_data_frame_option.ul_fsedge = SSC_TFMR_FSEDGE_POSITIVE;
/* Configure the SSC transmitter to I2S mode. */
ssc_set_transmitter(SSC, &tx_clk_option, &tx_data_frame_option);
/* Disable transmitter first */
ssc_disable_tx(SSC);
/* Disable All Interrupt */
ssc_disable_interrupt(SSC, 0xFFFFFFFF);
}
