static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *busdev;
SSIBus *spi;
int i;
dev = qdev_create(NULL, "xilinx,spips");
qdev_init_nofail(dev);
busdev = sysbus_from_qdev(dev);
sysbus_mmio_map(busdev, 0, base_addr);
sysbus_connect_irq(busdev, 0, irq);
spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
for (i = 0; i < NUM_SPI_FLASHES; ++i) {
qemu_irq cs_line;
dev = ssi_create_slave_no_init(spi, "m25p80");
qdev_prop_set_string(dev, "partname", "n25q128");
qdev_init_nofail(dev);
cs_line = qdev_get_gpio_in(dev, 0);
sysbus_connect_irq(busdev, i+1, cs_line);
}
}
static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
bool is_qspi)
{
DeviceState *dev;
SysBusDevice *busdev;
SSIBus *spi;
DeviceState *flash_dev;
int i, j;
int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
dev = qdev_create(NULL, "xilinx,spips");
qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
qdev_prop_set_uint8(dev, "num-busses", num_busses);
qdev_init_nofail(dev);
busdev = sysbus_from_qdev(dev);
sysbus_mmio_map(busdev, 0, base_addr);
if (is_qspi) {
sysbus_mmio_map(busdev, 1, 0xFC000000);
}
sysbus_connect_irq(busdev, 0, irq);
for (i = 0; i < num_busses; ++i) {
char bus_name[16];
qemu_irq cs_line;
snprintf(bus_name, 16, "spi%d", i);
spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
for (j = 0; j < num_ss; ++j) {
flash_dev = ssi_create_slave_no_init(spi, "m25p80");
qdev_prop_set_string(flash_dev, "partname", "n25q128");
qdev_init_nofail(flash_dev);
cs_line = qdev_get_gpio_in(flash_dev, 0);
sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
}
}
}
static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
Error **errp)
{
int i ;
for (i = 0; i < s->num_cs; ++i) {
AspeedSMCFlash *fl = &s->flashes[i];
DriveInfo *dinfo = drive_get_next(IF_MTD);
qemu_irq cs_line;
fl->flash = ssi_create_slave_no_init(s->spi, flashtype);
if (dinfo) {
qdev_prop_set_drive(fl->flash, "drive", blk_by_legacy_dinfo(dinfo),
errp);
}
qdev_init_nofail(fl->flash);
cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
}
}
static void
petalogix_ml605_init(QEMUMachineInitArgs *args)
{
ram_addr_t ram_size = args->ram_size;
const char *cpu_model = args->cpu_model;
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev, *dma, *eth0;
MicroBlazeCPU *cpu;
SysBusDevice *busdev;
CPUMBState *env;
DriveInfo *dinfo;
int i;
hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
if (cpu_model == NULL) {
cpu_model = "microblaze";
}
cpu = cpu_mb_init(cpu_model);
env = &cpu->env;
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, "petalogix_ml605.lmb_bram",
LMB_BRAM_SIZE);
vmstate_register_ram_global(phys_lmb_bram);
memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
memory_region_init_ram(phys_ram, "petalogix_ml605.ram", ram_size);
vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(address_space_mem, ddr_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* 5th parameter 2 means bank-width
* 10th paremeter 0 means little-endian */
pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_ml605.flash", FLASH_SIZE,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16,
2, 0x89, 0x18, 0x0000, 0x0, 0);
cpu_irq = microblaze_pic_init_cpu(env);
dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 4);
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
}
serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
irq[5], 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 100 Mhz. */
xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 1000000);
/* axi ethernet and dma initialization. */
dma = qdev_create(NULL, "xlnx.axi-dma");
/* FIXME: attach to the sysbus instead */
object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
"xilinx-dma", OBJECT(dma), NULL);
eth0 = xilinx_axiethernet_create(&nd_table[0], STREAM_SLAVE(dma),
0x82780000, irq[3], 0x1000, 0x1000);
xilinx_axiethernetdma_init(dma, STREAM_SLAVE(eth0),
0x84600000, irq[1], irq[0], 100 * 1000000);
{
SSIBus *spi;
dev = qdev_create(NULL, "xlnx.xps-spi");
qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0x40a00000);
sysbus_connect_irq(busdev, 0, irq[4]);
spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
for (i = 0; i < NUM_SPI_FLASHES; i++) {
qemu_irq cs_line;
dev = ssi_create_slave_no_init(spi, "m25p80");
qdev_prop_set_string(dev, "partname", "n25q128");
qdev_init_nofail(dev);
cs_line = qdev_get_gpio_in(dev, 0);
sysbus_connect_irq(busdev, i+1, cs_line);
}
}
microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
}
static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine)
{
int i;
uint64_t ram_size = machine->ram_size;
/* Create the memory region to pass to the SoC */
if (ram_size > XLNX_ZYNQMP_MAX_RAM_SIZE) {
error_report("ERROR: RAM size 0x%" PRIx64 " above max supported of "
"0x%llx", ram_size,
XLNX_ZYNQMP_MAX_RAM_SIZE);
exit(1);
}
if (ram_size < 0x08000000) {
qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102",
ram_size);
}
memory_region_allocate_system_memory(&s->ddr_ram, NULL, "ddr-ram",
ram_size);
object_initialize(&s->soc, sizeof(s->soc), TYPE_XLNX_ZYNQMP);
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
&error_abort);
object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram),
"ddr-ram", &error_abort);
object_property_set_bool(OBJECT(&s->soc), s->secure, "secure",
&error_fatal);
object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization",
&error_fatal);
object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
/* Create and plug in the SD cards */
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
BusState *bus;
DriveInfo *di = drive_get_next(IF_SD);
BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
DeviceState *carddev;
char *bus_name;
bus_name = g_strdup_printf("sd-bus%d", i);
bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
g_free(bus_name);
if (!bus) {
error_report("No SD bus found for SD card %d", i);
exit(1);
}
carddev = qdev_create(bus, TYPE_SD_CARD);
qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
object_property_set_bool(OBJECT(carddev), true, "realized",
&error_fatal);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
SSIBus *spi_bus;
DeviceState *flash_dev;
qemu_irq cs_line;
DriveInfo *dinfo = drive_get_next(IF_MTD);
gchar *bus_name = g_strdup_printf("spi%d", i);
spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
g_free(bus_name);
flash_dev = ssi_create_slave_no_init(spi_bus, "sst25wf080");
if (dinfo) {
qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
qdev_init_nofail(flash_dev);
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line);
}
for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) {
SSIBus *spi_bus;
DeviceState *flash_dev;
qemu_irq cs_line;
DriveInfo *dinfo = drive_get_next(IF_MTD);
int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS;
gchar *bus_name = g_strdup_printf("qspi%d", bus);
spi_bus = (SSIBus *)qdev_get_child_bus(DEVICE(&s->soc), bus_name);
g_free(bus_name);
flash_dev = ssi_create_slave_no_init(spi_bus, "n25q512a11");
if (dinfo) {
qdev_prop_set_drive(flash_dev, "drive", blk_by_legacy_dinfo(dinfo),
&error_fatal);
}
qdev_init_nofail(flash_dev);
cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line);
}
/* TODO create and connect IDE devices for ide_drive_get() */
xlnx_zcu102_binfo.ram_size = ram_size;
xlnx_zcu102_binfo.kernel_filename = machine->kernel_filename;
xlnx_zcu102_binfo.kernel_cmdline = machine->kernel_cmdline;
xlnx_zcu102_binfo.initrd_filename = machine->initrd_filename;
xlnx_zcu102_binfo.loader_start = 0;
arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo);
}
