void spi_format(spi_t *obj, int bits, int mode, int slave) { MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3))); ssp_disable(obj); int polarity = (mode & 0x2) ? 1 : 0; int phase = (mode & 0x1) ? 1 : 0; // set it up int DSS = bits - 1; // DSS (data select size) int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity int SPH = (phase) ? 1 : 0; // SPH - clock out phase uint32_t tmp = obj->spi->CFG; tmp &= ~((1 << 2) | (1 << 4) | (1 << 5)); tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2); obj->spi->CFG = tmp; // select frame length tmp = obj->spi->TXDATCTL; tmp &= ~(0xf << 24); tmp |= (DSS << 24); obj->spi->TXDATCTL = tmp; ssp_enable(obj); }
void spi_frequency(spi_t *obj, int hz) { ssp_disable(obj); // SPI1 runs from PCLK2, which runs at SystemCoreClock / 2. SPI2 and SPI3 // run from PCLK1, which runs at SystemCoreClock / 4. uint32_t PCLK = SystemCoreClock; switch ((int)obj->spi) { case SPI_1: PCLK = PCLK >> 1; break; case SPI_2: PCLK = PCLK >> 2; break; case SPI_3: PCLK = PCLK >> 2; break; } // Choose the baud rate divisor (between 2 and 256) uint32_t divisor = PCLK / hz; // Find the nearest power-of-2 divisor = divisor > 0 ? divisor-1 : 0; divisor |= divisor >> 1; divisor |= divisor >> 2; divisor |= divisor >> 4; divisor |= divisor >> 8; divisor |= divisor >> 16; divisor++; uint32_t baud_rate = __builtin_ffs(divisor) - 1; baud_rate = baud_rate > 0x7 ? 0x7 : baud_rate; obj->spi->CR1 &= ~(0x7 << 3); obj->spi->CR1 |= baud_rate << 3; ssp_enable(obj); }
void spi_format(spi_t *obj, int bits, int mode, int slave) { MBED_ASSERT(((bits >= 4) && (bits <= 16)) && ((mode >= 0) && (mode <= 3))); ssp_disable(obj); int polarity = (mode & 0x2) ? 1 : 0; int phase = (mode & 0x1) ? 1 : 0; // set it up int DSS = bits - 1; // DSS (data select size) int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity int SPH = (phase) ? 1 : 0; // SPH - clock out phase int FRF = 0; // FRF (frame format) = SPI uint32_t tmp = obj->spi->CR0; tmp &= ~(0xFFFF); tmp |= DSS << 0 | FRF << 4 | SPO << 6 | SPH << 7; obj->spi->CR0 = tmp; tmp = obj->spi->CR1; tmp &= ~(0xD); tmp |= 0 << 0 // LBM - loop back mode - off | ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave | 0 << 3; // SOD - slave output disable - na obj->spi->CR1 = tmp; ssp_enable(obj); }
void spi_frequency(spi_t *obj, int hz) { ssp_disable(obj); uint32_t PCLK = SystemCoreClock; int prescaler; for (prescaler = 2; prescaler <= 254; prescaler += 2) { int prescale_hz = PCLK / prescaler; // calculate the divider int divider = floor(((float)prescale_hz / (float)hz) + 0.5f); // check we can support the divider if (divider < 256) { // prescaler obj->spi->CPSR = prescaler; // divider obj->spi->CR0 &= ~(0xFFFF << 8); obj->spi->CR0 |= (divider - 1) << 8; ssp_enable(obj); return; } } error("Couldn't setup requested SPI frequency"); }
void spi_frequency(spi_t *obj, int hz) { ssp_disable(obj); uint32_t PCLK = SystemCoreClock; obj->spi->DIV = PCLK/hz - 1; obj->spi->DLY = 0; ssp_enable(obj); }
static int ad_probe(struct platform_device *pdev) { struct ad7877_platform_data *pdata = pdev->dev.platform_data; struct ad7877 *ad; int ret; int i; // Initialize ad data structure. ad = kzalloc(sizeof(*ad), GFP_KERNEL); if (!ad) return -ENOMEM; init_completion(&ad->comp); ret = request_irq(pdata->dav_irq, davirq , IRQF_DISABLED | IRQF_TRIGGER_FALLING , "ad7877-dav", ad); if (ret) { kfree(ad); return ret; } ret = ssp_init(&ad->ssp, 1, 0); if (ret) { printk(KERN_ERR "Unable to register SSP handler!\n"); free_irq(pdata->dav_irq, ad); kfree(ad); return ret; } platform_set_drvdata(pdev, ad); ssp_disable(&ad->ssp); ssp_config(&ad->ssp, SSCR0_DataSize(16), 0, 0, SSCR0_SerClkDiv(6)); ssp_enable(&ad->ssp); initChip(ad); for (i = 0; i < ARRAY_SIZE(acdevs); i++) { acdevs[i].sense = sense; ret = adc_classdev_register(&pdev->dev, &acdevs[i]); if (ret) { printk("ad7877: failed to register adc class " "device %s\n", acdevs[i].name); goto adc_cdev_register_failed; } } return 0; adc_cdev_register_failed: while (--i >= 0) adc_classdev_unregister(&acdevs[i]); return ret; }
static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; struct ssp_priv *priv = cpu_dai->private_data; struct ssp_device *ssp = priv->ssp; if (!cpu_dai->active) { ssp_disable(ssp); clk_disable(ssp->clk); } kfree(snd_soc_dai_get_dma_data(cpu_dai, substream)); snd_soc_dai_set_dma_data(cpu_dai, substream, NULL); }
static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; struct ssp_priv *priv = cpu_dai->private_data; if (!cpu_dai->active) { ssp_disable(&priv->dev); clk_disable(priv->dev.ssp->clk); } if (cpu_dai->dma_data) { kfree(cpu_dai->dma_data); cpu_dai->dma_data = NULL; } }
static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai) { struct ssp_priv *priv = cpu_dai->private_data; struct ssp_device *ssp = priv->ssp; if (!cpu_dai->active) clk_enable(ssp->clk); priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0); priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1); priv->to = __raw_readl(ssp->mmio_base + SSTO); priv->psp = __raw_readl(ssp->mmio_base + SSPSP); ssp_disable(ssp); clk_disable(ssp->clk); return 0; }
void spi_format(spi_t *obj, int bits, int mode, int slave) { MBED_ASSERT(((bits == 8) || (bits == 16)) && ((mode >= 0) && (mode <= 3))); ssp_disable(obj); int polarity = (mode & 0x2) ? 1 : 0; int phase = (mode & 0x1) ? 1 : 0; obj->spi->CR1 &= ~0x807; obj->spi->CR1 |= ((phase) ? 1 : 0) << 0 | ((polarity) ? 1 : 0) << 1 | ((slave) ? 0: 1) << 2 | ((bits == 16) ? 1 : 0) << 11; if (obj->spi->SR & SPI_SR_MODF) { obj->spi->CR1 = obj->spi->CR1; } ssp_enable(obj); }
static int pxa_ssp_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; struct ssp_priv *priv = cpu_dai->private_data; struct ssp_device *ssp = priv->ssp; int ret = 0; if (!cpu_dai->active) { clk_enable(ssp->clk); ssp_disable(ssp); } kfree(snd_soc_dai_get_dma_data(cpu_dai, substream)); snd_soc_dai_set_dma_data(cpu_dai, substream, NULL); return ret; }
static int pxa_ssp_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; struct ssp_priv *priv = cpu_dai->private_data; int ret = 0; if (!cpu_dai->active) { priv->dev.port = cpu_dai->id + 1; priv->dev.irq = NO_IRQ; clk_enable(priv->dev.ssp->clk); ssp_disable(&priv->dev); } if (cpu_dai->dma_data) { kfree(cpu_dai->dma_data); cpu_dai->dma_data = NULL; } return ret; }
void spi_frequency(spi_t *obj, int hz) { ssp_disable(obj); // setup the spi clock diveder to /1 #if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) switch ((int)obj->spi) { case SPI_0: LPC_SC->PCLKSEL1 &= ~(3 << 10); LPC_SC->PCLKSEL1 |= (1 << 10); break; case SPI_1: LPC_SC->PCLKSEL0 &= ~(3 << 20); LPC_SC->PCLKSEL0 |= (1 << 20); break; } #endif uint32_t PCLK = SystemCoreClock; int prescaler; for (prescaler = 2; prescaler <= 254; prescaler += 2) { int prescale_hz = PCLK / prescaler; // calculate the divider int divider = floor(((float)prescale_hz / (float)hz) + 0.5); // check we can support the divider if (divider < 256) { // prescaler obj->spi->CPSR = prescaler; // divider obj->spi->CR0 &= ~(0xFFFF << 8); obj->spi->CR0 |= (divider - 1) << 8; ssp_enable(obj); return; } } error("Couldn't setup requested SPI frequency"); }
void palmtt3_ssp_suspend(void) { ssp_disable(&palmtt3_ssp_dev); ssp_save_state(&palmtt3_ssp_dev,&ssp1); // FIXME power off TSC2101? }
static int __init a716_ssp_probe(struct platform_device *pdev) { int ret; if (!machine_is_a716()) { return -ENODEV; } a716_gpo_set(0x4000); ret = ssp_init(&a716_ssp_dev, 1, 0); if (ret) { printk(KERN_ERR "Unable to register SSP handler!\n"); return ret; } else { ssp_disable(&a716_ssp_dev); ssp_config(&a716_ssp_dev, (SSCR0_National | 0x0b), 0, 0, SSCR0_SerClkDiv(36)); ssp_enable(&a716_ssp_dev); } a716_ssp_putget(CTRL_YPOS | CTRL_START); mdelay(1); a716_ssp_putget(CTRL_Z1POS | CTRL_START); mdelay(1); a716_ssp_putget(CTRL_Z2POS | CTRL_START); mdelay(1); a716_ssp_putget(CTRL_XPOS | CTRL_START); init_timer(&timer_pen); timer_pen.function = a716_ts_timer; timer_pen.data = (unsigned long)NULL; idev = input_allocate_device(); if (!idev) return -ENOMEM; idev->name = "ad7873"; idev->phys = "touchscreen/ad7873"; set_bit(EV_ABS, idev->evbit); set_bit(EV_KEY, idev->evbit); set_bit(ABS_X, idev->absbit); set_bit(ABS_Y, idev->absbit); set_bit(ABS_PRESSURE, idev->absbit); set_bit(BTN_TOUCH, idev->keybit); idev->absmax[ABS_PRESSURE] = 1; idev->absmin[ABS_X] = 212; idev->absmin[ABS_Y] = 180; idev->absmax[ABS_X] = 3880; idev->absmax[ABS_Y] = 3940; input_register_device(idev); touch_pressed = 0; irq_disable = 0; set_irq_type(IRQ_GPIO(GPIO_NR_A716_STYLUS_IRQ_N), IRQT_FALLING); request_irq(IRQ_GPIO(GPIO_NR_A716_STYLUS_IRQ_N), a716_stylus, SA_SAMPLE_RANDOM, "ad7873 stylus", NULL); return 0; }