/****************************************************************************
* M68HC05EG section
****************************************************************************/
static CPU_INIT( m68hc05eg )
{
m6805_Regs *cpustate = get_safe_token(device);
state_register(cpustate, "m68hc05eg", device);
cpustate->irq_callback = irqcallback;
cpustate->device = device;
}
/****************************************************************************
* HD63705 section
****************************************************************************/
static CPU_INIT( hd63705 )
{
m6805_Regs *cpustate = get_safe_token(device);
state_register(cpustate, "hd63705", device);
cpustate->irq_callback = irqcallback;
cpustate->device = device;
}
int cpu_init()
{
palticks = 0;
cpu_disassemble_init();
state_register(B_CPU,cpu_state);
return(0);
}
static CPU_INIT( m6805 )
{
m6805_Regs *cpustate = get_safe_token(device);
state_register(cpustate, "m6805", device);
cpustate->irq_callback = irqcallback;
cpustate->device = device;
cpustate->program = device->space(AS_PROGRAM);
cpustate->direct = &cpustate->program->direct();
}
void hd63705_init(void)
{
int cpu = cpu_getactivecpu();
state_register("hd63705");
state_save_register_INT32("hd63705",cpu,"IRQ1_STATE", &m6805.irq_state[0], 1);
state_save_register_INT32("hd63705",cpu,"IRQ2_STATE", &m6805.irq_state[1], 1);
state_save_register_INT32("hd63705",cpu,"TIMER1_STATE", &m6805.irq_state[2], 1);
state_save_register_INT32("hd63705",cpu,"TIMER2_STATE", &m6805.irq_state[3], 1);
state_save_register_INT32("hd63705",cpu,"TIMER3_STATE", &m6805.irq_state[4], 1);
state_save_register_INT32("hd63705",cpu,"PCI_STATE", &m6805.irq_state[5], 1);
state_save_register_INT32("hd63705",cpu,"SCI_STATE", &m6805.irq_state[6], 1);
state_save_register_INT32("hd63705",cpu,"ADCONV_STATE", &m6805.irq_state[7], 1);
}
int genie_load()
{
char biosfile[1024];
//if the rom isnt loaded, we need to do that now
if(genierom == 0) {
//clear the string
memset(biosfile,0,1024);
//parse the bios path
config_get_eval_string(biosfile,"path.bios");
//append the path seperator
str_appendchar(biosfile,PATH_SEPERATOR);
//append the bios filename
strcat(biosfile,config_get_string("nes.gamegenie.bios"));
//try to load bios from the bios directory
if(genie_loadrom(biosfile) != 0) {
//see if bios is in the current directory
if(genie_loadrom(config_get_string("nes.gamegenie.bios")) != 0) {
return(1);
}
}
//register the save state stuff
state_register(B_GG,genie_state);
}
//load in the genie mapper
nes->mapper = &mapperB_GENIE;
return(0);
}
void nes_state::machine_start()
{
for (int i = 0; i < 9; i++)
{
char str[7];
sprintf(str, "FCKEY%i", i);
m_io_fckey[i] = ioport(str);
}
for (int i = 0; i < 13; i++)
{
char str[9];
sprintf(str, "SUBKEY%i", i);
m_io_subkey[i] = ioport(str);
}
for (int i = 0; i < 4; i++)
{
char str[8];
sprintf(str, "PAD%i", i + 1);
m_io_pad[i] = ioport(str);
sprintf(str, "MAH%i", i);
m_io_mahjong[i] = ioport(str);
sprintf(str, "FT_COL%i", i);
m_io_ftrainer[i] = ioport(str);
}
m_io_ctrlsel = ioport("CTRLSEL");
m_io_exp = ioport("EXP");
m_io_paddle = ioport("PADDLE");
m_io_paddle_btn = ioport("PADDLE_BUTTON");
m_io_cc_left = ioport("CC_LEFT");
m_io_cc_right = ioport("CC_RIGHT");
m_io_zapper1_t = ioport("ZAPPER1_T");
m_io_zapper1_x = ioport("ZAPPER1_X");
m_io_zapper1_y = ioport("ZAPPER1_Y");
m_io_zapper2_t = ioport("ZAPPER2_T");
m_io_zapper2_x = ioport("ZAPPER2_X");
m_io_zapper2_y = ioport("ZAPPER2_Y");
m_io_powerpad[0] = ioport("POWERPAD1");
m_io_powerpad[1] = ioport("POWERPAD2");
address_space &space = m_maincpu->space(AS_PROGRAM);
// CIRAM (Character Internal RAM)
// NES has 2KB of internal RAM which can be used to fill the 4x1KB banks of PPU RAM at $2000-$2fff
// Line A10 is exposed to the carts, so that games can change CIRAM mapping in PPU (we emulate this with the set_nt_mirroring
// function). CIRAM can also be disabled by the game (if e.g. VROM or cart RAM has to be used in PPU...
m_ciram = auto_alloc_array(machine(), UINT8, 0x800);
// other pointers got set in the loading routine, because they 'belong' to the cart itself
if (m_cartslot && m_cartslot->m_cart)
{
// Set up memory handlers
space.install_read_handler(0x4100, 0x5fff, read8_delegate(FUNC(nes_cart_slot_device::read_l), (nes_cart_slot_device *)m_cartslot));
space.install_write_handler(0x4100, 0x5fff, write8_delegate(FUNC(nes_cart_slot_device::write_l), (nes_cart_slot_device *)m_cartslot));
space.install_read_handler(0x6000, 0x7fff, read8_delegate(FUNC(nes_cart_slot_device::read_m), (nes_cart_slot_device *)m_cartslot));
space.install_write_handler(0x6000, 0x7fff, write8_delegate(FUNC(nes_cart_slot_device::write_m), (nes_cart_slot_device *)m_cartslot));
space.install_read_bank(0x8000, 0x9fff, "prg0");
space.install_read_bank(0xa000, 0xbfff, "prg1");
space.install_read_bank(0xc000, 0xdfff, "prg2");
space.install_read_bank(0xe000, 0xffff, "prg3");
space.install_write_handler(0x8000, 0xffff, write8_delegate(FUNC(nes_cart_slot_device::write_h), (nes_cart_slot_device *)m_cartslot));
m_cartslot->pcb_start(m_ciram);
m_cartslot->m_cart->pcb_reg_postload(machine());
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0, 0x1fff, read8_delegate(FUNC(device_nes_cart_interface::chr_r),m_cartslot->m_cart), write8_delegate(FUNC(device_nes_cart_interface::chr_w),m_cartslot->m_cart));
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(device_nes_cart_interface::nt_r),m_cartslot->m_cart), write8_delegate(FUNC(device_nes_cart_interface::nt_w),m_cartslot->m_cart));
m_ppu->set_scanline_callback(ppu2c0x_scanline_delegate(FUNC(device_nes_cart_interface::scanline_irq),m_cartslot->m_cart));
m_ppu->set_hblank_callback(ppu2c0x_hblank_delegate(FUNC(device_nes_cart_interface::hblank_irq),m_cartslot->m_cart));
m_ppu->set_latch(ppu2c0x_latch_delegate(FUNC(device_nes_cart_interface::ppu_latch),m_cartslot->m_cart));
// install additional handlers (read_h, read_ex, write_ex)
if (m_cartslot->get_pcb_id() == STD_EXROM || m_cartslot->get_pcb_id() == STD_NROM368
|| m_cartslot->get_pcb_id() == GG_NROM || m_cartslot->get_pcb_id() == CAMERICA_ALADDIN || m_cartslot->get_pcb_id() == SUNSOFT_DCS
|| m_cartslot->get_pcb_id() == BANDAI_DATACH || m_cartslot->get_pcb_id() == BANDAI_KARAOKE || m_cartslot->get_pcb_id() == BTL_2A03_PURITANS || m_cartslot->get_pcb_id() == AVE_MAXI15
|| m_cartslot->get_pcb_id() == KAISER_KS7022 || m_cartslot->get_pcb_id() == KAISER_KS7031 || m_cartslot->get_pcb_id() == BMC_VT5201
|| m_cartslot->get_pcb_id() == UNL_LH32 || m_cartslot->get_pcb_id() == UNL_LH10 || m_cartslot->get_pcb_id() == UNL_2708
|| m_cartslot->get_pcb_id() == UNL_43272 || m_cartslot->get_pcb_id() == BMC_G63IN1 || m_cartslot->get_pcb_id() == BMC_8157
|| m_cartslot->get_pcb_id() == BMC_GOLD150 || m_cartslot->get_pcb_id() == BMC_CH001
|| m_cartslot->get_pcb_id() == BMC_70IN1 || m_cartslot->get_pcb_id() == BMC_800IN1)
{
logerror("read_h installed!\n");
space.install_read_handler(0x8000, 0xffff, read8_delegate(FUNC(nes_cart_slot_device::read_h), (nes_cart_slot_device *)m_cartslot));
}
if (m_cartslot->get_pcb_id() == BTL_SMB2JB || m_cartslot->get_pcb_id() == UNL_AC08 || m_cartslot->get_pcb_id() == UNL_SMB2J || m_cartslot->get_pcb_id() == BTL_09034A)
{
logerror("write_ex installed!\n");
space.install_write_handler(0x4020, 0x40ff, write8_delegate(FUNC(nes_cart_slot_device::write_ex), (nes_cart_slot_device *)m_cartslot));
}
if (m_cartslot->get_pcb_id() == KAISER_KS7017 || m_cartslot->get_pcb_id() == UNL_603_5052)
{
logerror("write_ex & read_ex installed!\n");
space.install_read_handler(0x4020, 0x40ff, read8_delegate(FUNC(nes_cart_slot_device::read_ex), (nes_cart_slot_device *)m_cartslot));
space.install_write_handler(0x4020, 0x40ff, write8_delegate(FUNC(nes_cart_slot_device::write_ex), (nes_cart_slot_device *)m_cartslot));
}
}
else if (m_disk_expansion) // if there is Disk Expansion and no cart has been loaded, setup memory accordingly
{
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0, 0x1fff, read8_delegate(FUNC(nes_state::fds_chr_r),this), write8_delegate(FUNC(nes_state::fds_chr_w),this));
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(nes_state::fds_nt_r),this), write8_delegate(FUNC(nes_state::fds_nt_w),this));
if (!m_fds_ram)
m_fds_ram = auto_alloc_array(machine(), UINT8, 0x8000);
if (!m_vram)
m_vram = auto_alloc_array(machine(), UINT8, 0x2000);
space.install_read_handler(0x4030, 0x403f, read8_delegate(FUNC(nes_state::nes_fds_r),this));
space.install_read_bank(0x6000, 0xdfff, "fdsram");
space.install_read_bank(0xe000, 0xffff, "bank1");
space.install_write_handler(0x4020, 0x402f, write8_delegate(FUNC(nes_state::nes_fds_w),this));
space.install_write_bank(0x6000, 0xdfff, "fdsram");
membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base() + 0xe000);
membank("fdsram")->set_base(m_fds_ram);
}
state_register();
}
void m68705_init(void)
{
state_register("m68705");
}
/* Generate interrupts */
static void Interrupt(void)
{
/* the 6805 latches interrupt requests internally, so we don't clear */
/* pending_interrupts until the interrupt is taken, no matter what the */
/* external IRQ pin does. */
#if (HAS_HD63705)
if( (m6805.pending_interrupts & (1<<HD63705_INT_NMI)) != 0)
{
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
RM16( 0x1ffc, &pPC);
change_pc(PC);
m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI);
m6805_ICount -= 11;
}
else if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#else
if( (m6805.pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#endif
{
/* standard IRQ */
/*#if (HAS_HD63705) */
/* if(SUBTYPE!=SUBTYPE_HD63705) */
/*#endif */
/* PC |= ~AMASK; */
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
#if (HAS_HD63705)
if(SUBTYPE==SUBTYPE_HD63705)
{
/* Need to add emulation of other interrupt sources here KW-2/4/99 */
/* This is just a quick patch for Namco System 2 operation */
if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1);
RM16( 0x1ff8, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2);
RM16( 0x1fec, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV);
RM16( 0x1fea, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1);
RM16( 0x1ff6, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2);
RM16( 0x1ff4, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3);
RM16( 0x1ff2, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI);
RM16( 0x1ff0, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI);
RM16( 0x1fee, &pPC);
change_pc(PC);
}
}
else
#endif
{
RM16( 0xffff - 5, &pPC );
change_pc(PC);
}
} /* CC & IFLAG */
m6805.pending_interrupts &= ~(1<<M6805_IRQ_LINE);
}
m6805_ICount -= 11;
}
}
static void state_register(const char *type)
{
int cpu = cpu_getactivecpu();
state_save_register_UINT8(type, cpu, "A", &A, 1);
state_save_register_UINT16(type, cpu, "PC", &PC, 1);
state_save_register_UINT16(type, cpu, "S", &S, 1);
state_save_register_UINT8(type, cpu, "X", &X, 1);
state_save_register_UINT8(type, cpu, "CC", &CC, 1);
state_save_register_UINT16(type, cpu, "PENDING", &m6805.pending_interrupts, 1);
state_save_register_INT32(type, cpu, "IRQ_STATE", &m6805.irq_state[0], 1);
}
static void m6805_init(void)
{
state_register("m6805");
}
static void hd63705_init(int index, int clock, const void *config, int (*irqcallback)(int))
{
state_register("hd63705", index);
m6805.irq_callback = irqcallback;
}
/* Generate interrupts */
static void Interrupt(void)
{
/* the 6805 latches interrupt requests internally, so we don't clear */
/* pending_interrupts until the interrupt is taken, no matter what the */
/* external IRQ pin does. */
#if (HAS_HD63705)
if( (m6805.pending_interrupts & (1<<HD63705_INT_NMI)) != 0)
{
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
RM16( 0x1ffc, &pPC);
change_pc(PC);
m6805.pending_interrupts &= ~(1<<HD63705_INT_NMI);
m6805_ICount -= 11;
}
else if( (m6805.pending_interrupts & ((1<<M6805_IRQ_LINE)|HD63705_INT_MASK)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#else
if( (m6805.pending_interrupts & (1<<M6805_IRQ_LINE)) != 0 ) {
if ( (CC & IFLAG) == 0 ) {
#endif
{
/* standard IRQ */
//#if (HAS_HD63705)
// if(SUBTYPE!=SUBTYPE_HD63705)
//#endif
// PC |= ~AMASK;
PUSHWORD(m6805.pc);
PUSHBYTE(m6805.x);
PUSHBYTE(m6805.a);
PUSHBYTE(m6805.cc);
SEI;
/* no vectors supported, just do the callback to clear irq_state if needed */
if (m6805.irq_callback)
(*m6805.irq_callback)(0);
#if (HAS_HD63705)
if(SUBTYPE==SUBTYPE_HD63705)
{
/* Need to add emulation of other interrupt sources here KW-2/4/99 */
/* This is just a quick patch for Namco System 2 operation */
if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ1);
RM16( 0x1ff8, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_IRQ2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_IRQ2);
RM16( 0x1fec, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_ADCONV))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_ADCONV);
RM16( 0x1fea, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER1))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER1);
RM16( 0x1ff6, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER2))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER2);
RM16( 0x1ff4, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_TIMER3))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_TIMER3);
RM16( 0x1ff2, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_PCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_PCI);
RM16( 0x1ff0, &pPC);
change_pc(PC);
}
else if((m6805.pending_interrupts&(1<<HD63705_INT_SCI))!=0)
{
m6805.pending_interrupts &= ~(1<<HD63705_INT_SCI);
RM16( 0x1fee, &pPC);
change_pc(PC);
}
}
else
#endif
{
RM16( 0xffff - 5, &pPC );
change_pc(PC);
}
} // CC & IFLAG
m6805.pending_interrupts &= ~(1<<M6805_IRQ_LINE);
}
m6805_ICount -= 11;
}
}
static void state_register(const char *type, int index)
{
state_save_register_item(type, index, A);
state_save_register_item(type, index, PC);
state_save_register_item(type, index, S);
state_save_register_item(type, index, X);
state_save_register_item(type, index, CC);
state_save_register_item(type, index, m6805.pending_interrupts);
state_save_register_item_array(type, index, m6805.irq_state);
}
static void m6805_init(int index, int clock, const void *config, int (*irqcallback)(int))
{
state_register("m6805", index);
m6805.irq_callback = irqcallback;
}
