static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev)
{
uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET);
val |= ATIM_CR1_CEN;
stm32_tim_reload_counter(dev);
stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
}
static stm32_cap_flags_t stm32_cap_getflags(FAR struct stm32_cap_dev_s *dev)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint16_t regval = 0;
stm32_cap_flags_t flags = 0;
regval = stm32_getreg16(priv, STM32_BTIM_SR_OFFSET);
if (regval & ATIM_SR_UIF)
{
flags |= STM32_CAP_FLAG_IRQ_COUNTER;
}
if (regval & ATIM_SR_CC1IF)
{
flags |= STM32_CAP_FLAG_IRQ_CH_1;
}
if (regval & ATIM_SR_CC2IF)
{
flags |= STM32_CAP_FLAG_IRQ_CH_2;
}
if (regval & ATIM_SR_CC3IF)
{
flags |= STM32_CAP_FLAG_IRQ_CH_3;
}
if (regval & ATIM_SR_CC4IF)
{
flags |= STM32_CAP_FLAG_IRQ_CH_4;
}
if (regval & ATIM_SR_CC1OF)
{
flags |= STM32_CAP_FLAG_OF_CH_1;
}
if (regval & ATIM_SR_CC2OF)
{
flags |= STM32_CAP_FLAG_OF_CH_2;
}
if (regval & ATIM_SR_CC3OF)
{
flags |= STM32_CAP_FLAG_OF_CH_3;
}
if (regval & ATIM_SR_CC4OF)
{
flags |= STM32_CAP_FLAG_OF_CH_4;
}
return flags;
}
static uint32_t stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev, uint8_t channel)
{
const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint32_t offset;
DEBUGASSERT(dev != NULL);
switch (channel)
{
case STM32_CAP_CHANNEL_COUNTER:
offset = STM32_GTIM_CNT_OFFSET;
break;
#ifdef HAVE_CH1IN
case 1:
offset = STM32_GTIM_CCR1_OFFSET;
break;
#endif
#ifdef HAVE_CH2IN
case 2:
offset = STM32_GTIM_CCR2_OFFSET;
break;
#endif
#ifdef HAVE_CH3IN
case 3:
offset = STM32_GTIM_CCR3_OFFSET;
break;
#endif
#ifdef HAVE_CH4IN
case 4:
offset = STM32_GTIM_CCR4_OFFSET;
break;
#endif
default:
return ERROR;
}
if (priv->base == STM32_TIM2_BASE || priv->base == STM32_TIM5_BASE)
{
return stm32_getreg32(priv, offset);
}
return stm32_getreg16(priv, offset);
}
static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode)
{
uint16_t ccmr_val = 0;
uint16_t ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET);
uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET;
ASSERT(dev);
/* Further we use range as 0..3; if channel=0 it will also overflow here */
if (--channel > 4) return ERROR;
/* Assume that channel is disabled and polarity is active high */
ccer_val &= ~(3 << (channel << 2));
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
*/
#if STM32_NBTIM > 0
if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE
#endif
#if STM32_NBTIM > 1
|| ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE
#endif
#if STM32_NBTIM > 0
)
{
return ERROR;
}
#endif
/* Decode configuration */
switch (mode & STM32_TIM_CH_MODE_MASK)
{
case STM32_TIM_CH_DISABLED:
break;
case STM32_TIM_CH_OUTPWM:
ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) + ATIM_CCMR1_OC1PE;
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
break;
default:
return ERROR;
}
/* Set polarity */
if (mode & STM32_TIM_CH_POLARITY_NEG)
{
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
}
/* Define its position (shift) and get register offset */
if (channel & 1)
{
ccmr_val <<= 8;
}
if (channel > 1)
{
ccmr_offset = STM32_GTIM_CCMR2_OFFSET;
}
stm32_putreg16(dev, ccmr_offset, ccmr_val);
stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val);
/* set GPIO */
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#if CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
{
#if defined(GPIO_TIM2_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode);
break;
#endif
#if defined(GPIO_TIM2_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode);
break;
#endif
#if defined(GPIO_TIM2_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode);
break;
#endif
#if defined(GPIO_TIM2_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode);
break;
#endif
default:
return ERROR;
}
break;
#endif
#if CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
switch (channel)
{
#if defined(GPIO_TIM3_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode);
break;
#endif
#if defined(GPIO_TIM3_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode);
break;
#endif
#if defined(GPIO_TIM3_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode);
break;
#endif
#if defined(GPIO_TIM3_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode);
break;
#endif
default:
return ERROR;
}
break;
#endif
#if CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
switch (channel)
{
#if defined(GPIO_TIM4_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode);
break;
#endif
#if defined(GPIO_TIM4_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode);
break;
#endif
#if defined(GPIO_TIM4_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode);
break;
#endif
#if defined(GPIO_TIM4_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode);
break;
#endif
default:
return ERROR;
}
break;
#endif
#if CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
switch (channel)
{
#if defined(GPIO_TIM5_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode);
break;
#endif
#if defined(GPIO_TIM5_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode);
break;
#endif
#if defined(GPIO_TIM5_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode);
break;
#endif
#if defined(GPIO_TIM5_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode);
break;
#endif
default:
return ERROR;
}
break;
#endif
#if STM32_NATIM > 0
#if CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
switch (channel)
{
#if defined(GPIO_TIM1_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode);
break;
#endif
#if defined(GPIO_TIM1_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode);
break;
#endif
#if defined(GPIO_TIM1_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode);
break;
#endif
#if defined(GPIO_TIM1_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode);
break;
#endif
default:
return ERROR;
}
break;
#endif
#if CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
switch (channel)
{
#if defined(GPIO_TIM8_CH1OUT)
case 0:
stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode);
break;
#endif
#if defined(GPIO_TIM8_CH2OUT)
case 1:
stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode);
break;
#endif
#if defined(GPIO_TIM8_CH3OUT)
case 2:
stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode);
break;
#endif
#if defined(GPIO_TIM8_CH4OUT)
case 3:
stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode);
break;
#endif
default:
return ERROR;
}
break;
#endif
#endif
default:
return ERROR;
}
return OK;
}
static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev)
{
uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET);
val &= ~ATIM_CR1_CEN;
stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val);
}
static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev)
{
uint16_t val = stm32_getreg16(dev, STM32_BTIM_EGR_OFFSET);
val |= ATIM_EGR_UG;
stm32_putreg16(dev, STM32_BTIM_EGR_OFFSET, val);
}
