示例#1
0
void stdio_init(void)
{
	struct stm32_usart * uart = STM32_USART1;

	/* Enable GPIO */
	stm32_gpio_clock_en(STM32_GPIOA);

	/* Configure TX pin */
	stm32_gpio_mode(UART_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW);
	stm32_gpio_af(UART_TX, GPIO_AF7);

	/* Configure RX pin */
	stm32_gpio_mode(UART_RX, ALT_FUNC, PULL_UP);
	stm32_gpio_af(UART_RX, GPIO_AF7);

	stm32_usart_init(uart);
	stm32_usart_baudrate_set(uart, 115200);
	stm32_usart_mode_set(uart, SERIAL_8N1);
	stm32_usart_enable(uart);

	stm32_usart_write(uart, "Hello world!", 12);

	stderr = (struct file *)&stm32f_uart_file;
	stdin = stderr;
	stdout = stdin;
}
示例#2
0
void isink_init(void)
{
	struct stm32f_dac * dac = STM32_DAC;
	struct stm32f_tim * tim = STM32_TIM4;
	uint32_t div;

	stm32_gpio_clr(SINK1);
	stm32_gpio_clr(SINK2);
	stm32_gpio_clr(SINK3);
	stm32_gpio_clr(SINK4);
	stm32_gpio_mode(SINK1, OUTPUT, PUSH_PULL | SPEED_HIGH);
	stm32_gpio_mode(SINK2, OUTPUT, PUSH_PULL | SPEED_HIGH);
	stm32_gpio_mode(SINK3, OUTPUT, PUSH_PULL | SPEED_HIGH);
	stm32_gpio_mode(SINK4, OUTPUT, OPEN_DRAIN | SPEED_HIGH);
	stm32_gpio_af(SINK1, GPIO_AF2);
	stm32_gpio_af(SINK2, GPIO_AF2);
	stm32_gpio_af(SINK3, GPIO_AF2);

	/* Timer clock enable */
	stm32_clk_enable(STM32_RCC, STM32_CLK_TIM4);
	
	/* get the total divisior */
	div = (stm32f_tim1_hz + (FREQ_1MHZ / 2)) / FREQ_1MHZ;
	/* Timer configuration */
	tim->cr1 = 0;
	tim->psc = div - 1;
	tim->arr = 1;
	tim->ccmr1 = TIM_OC1M_PWM_MODE2 | TIM_OC2M_PWM_MODE2;
	tim->ccmr2 = TIM_OC3M_PWM_MODE2 | TIM_OC4M_PWM_MODE2;
	tim->ccer = TIM_CC1E | TIM_CC2E | TIM_CC3E | TIM_CC4E;
	//	TIM_CC1P | TIM_CC2P | TIM_CC3P | TIM_CC4P;
	tim->ccr1 = 1;
	tim->ccr2 = 1;
	tim->ccr3 = 1;
	tim->ccr4 = 1;


	tim->dier = TIM_UIE; /* Update interrupt enable */
	cm3_irq_pri_set(STM32_IRQ_TIM4, IRQ_PRIORITY_HIGH);
	/* Enable interrupt */
	cm3_irq_enable(STM32_IRQ_TIM4);

	/* I/O pins config */
	stm32_gpio_mode(IRATE, ANALOG, 0);
	stm32_gpio_clr(IRATE);

	/* DAC clock enable */
	stm32_clk_enable(STM32_RCC, STM32_CLK_DAC);

	/* DAC disable */
	dac->cr = 0;
	/* DAC configure */
	dac->cr = DAC_EN2;
	/* DAC channel 2 initial value */
	dac->dhr12r2 = 0;
	/* DAC channel 1 initial value */
	dac->dhr12r1 = 0;

	isink_drv.mode = -1;
}
示例#3
0
void io_init(void)
{
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOA);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOB);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOC);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOD);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE);

#if 0
	/* JTAG TRST Pin */
	stm32_gpio_mode(MODSW, INPUT, SPEED_LOW);
#endif

	/* USART5 TX */
	stm32_gpio_mode(UART5_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW);
	stm32_gpio_af(UART5_TX, GPIO_AF8);
	/* USART5 RX */
	stm32_gpio_mode(UART5_RX, ALT_FUNC, PULL_UP);
	stm32_gpio_af(UART5_RX, GPIO_AF8);

	/* USART6_TX */
	stm32_gpio_mode(UART6_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW);
	stm32_gpio_af(UART6_TX, GPIO_AF7);
	/* USART6_RX */
	stm32_gpio_mode(UART6_RX, ALT_FUNC, PULL_UP);
	stm32_gpio_af(UART6_RX, GPIO_AF7);

}
示例#4
0
void stdio_init(void)
{
	struct stm32_usart * uart = STM32_USART1;
#if defined(STM32F1X)
	struct stm32f_afio * afio = STM32F_AFIO;
#endif

	DCC_LOG(LOG_TRACE, "...");

	/* USART1_TX */
	stm32_gpio_mode(USART1_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW);

#if defined(STM32F1X)
	/* USART1_RX */
	stm32f_gpio_mode(USART1_RX, INPUT, PULL_UP);
	/* Use alternate pins for USART1 */
	afio->mapr |= AFIO_USART1_REMAP;
#elif defined(STM32F4X)
	stm32_gpio_mode(USART1_RX, ALT_FUNC, PULL_UP);
	stm32_gpio_af(USART1_RX, GPIO_AF7);
	stm32_gpio_af(USART1_TX, GPIO_AF7);
#endif

	stm32_usart_init(uart);
	stm32_usart_baudrate_set(uart, 115200);
	stm32_usart_mode_set(uart, SERIAL_8N1);
	stm32_usart_enable(uart);

	stdin = &stm32_uart1_file;
	stdout = &stm32_uart1_file;
	stderr = &stm32_uart1_file;
}
示例#5
0
void net_init(void)
{
	printf("%s():...\n", __func__);

	/* IO init */
	stm32_gpio_mode(USART2_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW);
	stm32_gpio_mode(USART2_RX, ALT_FUNC, PULL_UP);
	stm32_gpio_af(USART2_RX, GPIO_AF7);
	stm32_gpio_af(USART2_TX, GPIO_AF7);

	stm32_gpio_mode(LINK_TXEN, OUTPUT, PUSH_PULL | SPEED_LOW);
	stm32_gpio_mode(LINK_LOOP, OUTPUT, PUSH_PULL | SPEED_LOW);

	stm32_gpio_set(LINK_LOOP);
	stm32_gpio_set(LINK_TXEN);

	/* initialize the packet buffer pool */
	pktbuf_pool_init();

	/* DMA configuration for USART2 
	 * TX: DMA1, Stream6, Channel 4
	 * RX: DMA1, Stream5, Channel 4 
	 */

	/* Link init */
	rs485_init(&link, STM32_USART2, 1000, STM32F_DMA1, 
			   USART2_DMA_STRM_RX, USART2_DMA_CHAN_RX,
			   USART2_DMA_STRM_TX, USART2_DMA_CHAN_TX);

	cm3_irq_enable(STM32_IRQ_USART2);
}
示例#6
0
文件: net.c 项目: powertang/yard-ice
int net_init(void)
{
	tracef("%s():...", __func__);

	if (lattice_ice40_configure(ice40lp384_bin, sizeof_ice40lp384_bin) < 0) {
		trace("lattice_ice40_configure() failed!");
		return -1;
	}

	/* IO init */
	stm32_gpio_mode(RS485_RX, ALT_FUNC, PULL_UP);
	stm32_gpio_af(RS485_RX, GPIO_AF7);

	stm32_gpio_mode(RS485_TX, ALT_FUNC, PUSH_PULL | SPEED_MED);
	stm32_gpio_af(RS485_TX, GPIO_AF7);

#ifdef RS485_CK
	stm32_gpio_mode(RS485_CK, ALT_FUNC, PUSH_PULL | SPEED_MED);
	stm32_gpio_af(RS485_CK, GPIO_AF7);
#endif

#ifdef RS485_TRIG
	stm32_gpio_mode(RS485_TRIG, INPUT, PULL_UP);
#endif

#ifdef RS485_TXEN
	stm32_gpio_mode(RS485_TXEN, OUTPUT, PUSH_PULL | SPEED_MED);
	stm32_gpio_set(RS485_TXEN);
#endif

#ifdef RS485_LOOP
	stm32_gpio_mode(RS485_LOOP, OUTPUT, PUSH_PULL | SPEED_MED);
	stm32_gpio_set(RS485_LOOP);
#endif

#ifdef RS485_MODE
	stm32_gpio_mode(RS485_MODE, OUTPUT, PUSH_PULL | SPEED_LOW);
	stm32_gpio_set(RS485_MODE);
#endif


	if (!net.initialized) {
		/* Link init */
		rs485_init(&net.link, RS485_USART, RS485_LINK_SPEED, 
				   USART1_DMA, USART1_DMA_CHAN,
				   USART1_RX_DMA_STRM, USART1_TX_DMA_STRM);

		/* initialize the packet buffer pool */
		pktbuf_pool_init();

		net_recv_init();

		net.probe_flag = thinkos_flag_alloc();

		net.initialized = true;
	}


	return 0;
}
示例#7
0
struct serial_dev * serial_open(void)
{
    stm32_gpio_clk_en(STM32_GPIOC);

    /* UART TX */
    stm32_gpio_mode(UART_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW);
    stm32_gpio_af(UART_TX, GPIO_AF8);
    /* UART RX */
    stm32_gpio_mode(UART_RX, ALT_FUNC, PULL_UP);
    stm32_gpio_af(UART_RX, GPIO_AF8);

    return stm32f_uart6_serial_init(115200, SERIAL_8N1);
}
示例#8
0
/*
 * Initialize IO pins and SPI low level device 
 */
static int lattice_ice40_io_init(unsigned int freq)
{
	struct stm32f_spi * spi = STM32F_SPI3;
	unsigned int div;
	int br;

	/* Enable peripheral clock */
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOB);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOC);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE);
	stm32_clk_enable(STM32_RCC, STM32_CLK_SPI3);

	/* Configure IO pins */
	stm32_gpio_mode(ICE40_CDONE, INPUT, PULL_UP);

	stm32_gpio_set(ICE40_CRESET);
	stm32_gpio_mode(ICE40_CRESET, OUTPUT, SPEED_MED);

	stm32_gpio_set(ICE40_SPI_SS);
	stm32_gpio_mode(ICE40_SPI_SS, OUTPUT, SPEED_MED);

	stm32_gpio_mode(ICE40_SPI_SCK, ALT_FUNC, PUSH_PULL | SPEED_LOW);
	stm32_gpio_af(ICE40_SPI_SCK, GPIO_AF6);

	stm32_gpio_mode(ICE40_SPI_SDO, ALT_FUNC, PULL_UP);
	stm32_gpio_af(ICE40_SPI_SDO, GPIO_AF6);

	stm32_gpio_mode(ICE40_SPI_SDI, ALT_FUNC, PUSH_PULL | SPEED_LOW);
	stm32_gpio_af(ICE40_SPI_SDI, GPIO_AF6);

	/* Configure SPI */
	div = stm32_clk_hz(STM32_CLK_SPI3) / freq / 2;
	br = 31 - __clz(div);
	if (div > (1 << br))
		br++;

    DCC_LOG3(LOG_TRACE, "SPI freq=%d div=%d br=%d", freq, div, br);

	spi->cr1 = 0;
	spi->cr2 = 0;
	spi->i2scfgr = 0;
	spi->i2spr = 0;

	/* Master mode, MSB first */
	spi->cr1 = SPI_SPE | SPI_BR_SET(br) | SPI_MSTR | SPI_SSM | SPI_SSI;

	return 0;
}
示例#9
0
void stdio_init(void)
{
#if defined(STM32F2X)
	struct stm32_usart * uart = STM32_UART5;
#else
	struct stm32_usart * uart = STM32_USART1;
#endif
#if defined(STM32F1X)
	struct stm32f_afio * afio = STM32F_AFIO;
#endif

	/* Enable GPIO */
#if defined(STM32F2X)
	stm32_gpio_clock_en(STM32_GPIOC);
	stm32_gpio_clock_en(STM32_GPIOD);
#else
	stm32_gpio_clock_en(STM32_GPIOB);
#endif

	/* USART1_TX */
	stm32_gpio_mode(UART_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW);

#if defined(STM32F1X)
	/* USART1_RX */
	stm32_gpio_mode(UART_RX, INPUT, PULL_UP);
	/* Use alternate pins for USART1 */
	afio->mapr |= AFIO_USART1_REMAP;
#elif defined(STM32F4X)
	stm32_gpio_mode(UART_RX, ALT_FUNC, PULL_UP);
	stm32_gpio_af(UART_RX, GPIO_AF7);
	stm32_gpio_af(UART_TX, GPIO_AF7);
#elif defined(STM32F2X)
	stm32_gpio_mode(UART_RX, ALT_FUNC, PULL_UP);
	stm32_gpio_af(UART_RX, GPIO_AF8);
	stm32_gpio_af(UART_TX, GPIO_AF8);
#endif

	stm32_usart_init(uart);
	stm32_usart_baudrate_set(uart, 115200);
	stm32_usart_mode_set(uart, SERIAL_8N1);
	stm32_usart_enable(uart);

	stderr = &stm32f_uart_file;
	stdin = stderr;
	stdout = stdin;
}
示例#10
0
static void io_txd_cfg(struct stm32_gpio * gpio, int port, int af)
{
	stm32_gpio_clock_en(gpio);
	stm32_gpio_mode(gpio, port, ALT_FUNC, PUSH_PULL | SPEED_LOW);
#ifdef STM32F2X
	stm32_gpio_af(gpio, port, af);
#endif
}
示例#11
0
void stdio_init(void)
{
	struct stm32_usart * uart = STM32_UART5;

	stm32_gpio_clock_en(STM32_GPIOC);
	stm32_gpio_clock_en(STM32_GPIOD);
	stm32_gpio_mode(UART_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW);
	stm32_gpio_mode(UART_RX, ALT_FUNC, PULL_UP);
	stm32_gpio_af(UART_RX, GPIO_AF8);
	stm32_gpio_af(UART_TX, GPIO_AF8);

	stm32_usart_init(uart);
	stm32_usart_baudrate_set(uart, 115200);
	stm32_usart_mode_set(uart, SERIAL_8N1);
	stm32_usart_enable(uart);

	stderr = (struct file *)&stm32_uart_file;
	stdout = stderr;
	stdin = stdout;
}
示例#12
0
/* -------------------------------------------------------------------------
 * Test
 * ------------------------------------------------------------------------- */
void io_init(void)
{
	thinkos_udelay_factor(&udelay_factor);

	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOA);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOB);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOC);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOD);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE);

    /* USART5 TX */
    stm32_gpio_mode(UART5_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW);
    stm32_gpio_af(UART5_TX, GPIO_AF8);
    /* USART5 RX */
    stm32_gpio_mode(UART5_RX, ALT_FUNC, PULL_UP);
    stm32_gpio_af(UART5_RX, GPIO_AF8);

    stm32_gpio_mode(IO_RS485_RX, ALT_FUNC, PULL_UP);
    stm32_gpio_af(IO_RS485_RX, RS485_USART_AF);

    stm32_gpio_mode(IO_RS485_TX, ALT_FUNC, PUSH_PULL | SPEED_MED);
    stm32_gpio_af(IO_RS485_TX, RS485_USART_AF);

    stm32_gpio_mode(IO_RS485_MODE, OUTPUT, PUSH_PULL | SPEED_LOW);
    stm32_gpio_set(IO_RS485_MODE);

    /* USART6_TX */
    stm32_gpio_mode(UART6_TX, ALT_FUNC, PUSH_PULL | SPEED_LOW);
    stm32_gpio_af(UART6_TX, GPIO_AF7);
    /* USART6_RX */
    stm32_gpio_mode(UART6_RX, ALT_FUNC, PULL_UP);
    stm32_gpio_af(UART6_RX, GPIO_AF7);
}
示例#13
0
void stm32f_mco2_init(void)
{
	struct stm32_gpio * gpio = MCO2_GPIO;
	int pin = MCO2_PIN;

#ifdef STM32F_SYSCFG
	struct stm32f_syscfg * syscfg = STM32F_SYSCFG;
    /* enable I/O compensation cell */
	syscfg->cmpcr |= SYSCFG_CMP_EN;
#endif

	/* initial state is disabled */
	stm32_gpio_mode(gpio, pin, OUTPUT, PUSH_PULL | SPEED_HIGH);
	stm32_gpio_clk_en(gpio);
	stm32_gpio_af(gpio, pin, GPIO_AF0);
}
示例#14
0
void stm32f_fsmc_init(void)
{
	struct stm32f_fsmc * fsmc = STM32F_FSMC;

	DCC_LOG(LOG_TRACE, ".");

	/* Flexible static memory controller module clock enable */
	stm32_clk_enable(STM32_RCC, STM32_CLK_FSMC);

#if 0
	int i;

	/* Configure IO pins */
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOD);
	stm32_clk_enable(STM32_RCC, STM32_CLK_GPIOE);

	for (i = 0; i < sizeof(fsmc_io) / sizeof(gpio_io_t); i++) {
		gpio_io_t io = fsmc_io[i];
		stm32_gpio_mode(STM32_GPIO(io.port), io.pin, 
						 ALT_FUNC, PUSH_PULL | SPEED_HIGH);
		stm32_gpio_af(STM32_GPIO(io.port), io.pin, GPIO_AF12);
	}

	stm32_gpio_mode(STM32_GPIO(GPIOD), 6, INPUT, PUSH_PULL | SPEED_HIGH);
#endif

	fsmc->bcr1 = FSMC_CBURSTRW |	
		FSMC_WREN | 
		FSMC_BURSTEN | 
		FSMC_MWID_16 | 
		FSMC_MTYP_PSRAM | 
		FSMC_MUXEN | /* Address/Data multiplexed */
		FSMC_MBKEN |
		FSMC_WAITEN |
		FSMC_WAITPOL;
	
	fsmc->btr1 = FSMC_ACCMOD_A | FSMC_DATLAT_SET(0) |
		FSMC_CLKDIV_SET(3) | FSMC_BUSTURN_SET(0) |
		FSMC_DATAST_SET(0) | FSMC_ADDHDL_SET(0) |
		FSMC_ADDSET_SET(0);

	fsmc->bwtr1 = FSMC_ACCMOD_A | FSMC_DATLAT_SET(0) |
		FSMC_CLKDIV_SET(1) | FSMC_BUSTURN_SET(0) |
		FSMC_DATAST_SET(0) | FSMC_ADDHDL_SET(0) |
		FSMC_ADDSET_SET(0);
}
示例#15
0
int stm32f_spi_init(struct stm32f_spi * spi, 
					const struct stm32f_spi_io * spi_io, 
					unsigned int freq, unsigned int opt)
{
	struct stm32_rcc * rcc = STM32_RCC;
	gpio_io_t io;
	uint32_t div;
	int br;
	int id;

	if ((id = stm32f_spi_lookup(spi)) < 0) {
		/* invalid SPI ??? */
		return id;
	}

	/* Configure IO pins */
	io = spi_io->miso;
	stm32_gpio_clock_en(STM32_GPIO(io.port));
	stm32_gpio_mode(STM32_GPIO(io.port), io.pin, ALT_FUNC, 
					 PULL_UP | SPEED_MED);
	stm32_gpio_af(STM32_GPIO(io.port), io.pin, spi_cfg[id].af);

	io = spi_io->mosi;
	stm32_gpio_clock_en(STM32_GPIO(io.port));
	stm32_gpio_mode(STM32_GPIO(io.port), io.pin, ALT_FUNC, 
					 PUSH_PULL | SPEED_MED);
	stm32_gpio_af(STM32_GPIO(io.port), io.pin, spi_cfg[id].af);

	io = spi_io->sck;
	stm32_gpio_clock_en(STM32_GPIO(io.port));
	stm32_gpio_mode(STM32_GPIO(io.port), io.pin, ALT_FUNC, 
					 PUSH_PULL | SPEED_MED);
	stm32_gpio_af(STM32_GPIO(io.port), io.pin, spi_cfg[id].af);

	/* Enable peripheral clock */
	if (spi_cfg[id].apb2) {
		rcc->apb2enr |= (1 << spi_cfg[id].ckbit);
		div = stm32f_apb2_hz / freq / 2;
	} else {
		rcc->apb1enr |= (1 << spi_cfg[id].ckbit);
		div = stm32f_apb1_hz / freq / 2;
	}

	br = 31 - __clz(div);
	if (div > (1 << br)) {
		br++;
	}
    DCC_LOG3(LOG_TRACE, "SPI id=%d div=%d br=%d", id, div, br);

	spi->cr1 = 0;
	spi->cr2 = 0;
	spi->i2scfgr = 0;
	spi->i2spr = 0;

	spi->cr1 = SPI_SPE | SPI_BR_SET(br) | opt | SPI_SSM | SPI_SSI;

#if 0
	spi->cr1 = SPI_SPE | SPI_MSTR | SPI_SSM | SPI_SSI | \
			   SPI_BR_SET(br) | SPI_LSBFIRST;
#endif

	return id;
}