/**Function*************************************************************
Synopsis [Dumps the target AIG into the BENCH file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
char * ABC_GetNodeName( ABC_Manager mng, Abc_Obj_t * pNode )
{
char * pName = NULL;
if ( !stmm_lookup( mng->tNode2Name, (char *)pNode, (char **)&pName ) )
{
assert( 0 );
}
return pName;
}
/**Function*************************************************************
Synopsis [Adds a new target to the manager.]
Description [The meaning of the parameters are:
nog: number of gates that are in the targets,
names: name array of gates,
values: value array of the corresponding gates given in "names" to be solved.
The relation of them is AND.]
SideEffects []
SeeAlso []
***********************************************************************/
int ABC_AddTarget( ABC_Manager mng, int nog, char ** names, int * values )
{
Abc_Obj_t * pObj;
int i;
if ( nog < 1 )
{ printf( "ABC_AddTarget: The target has no gates.\n" ); return 0; }
// clear storage for the target
mng->nog = 0;
Vec_PtrClear( mng->vNodes );
Vec_IntClear( mng->vValues );
// save the target
for ( i = 0; i < nog; i++ )
{
if ( !stmm_lookup( mng->tName2Node, names[i], (char **)&pObj ) )
{ printf( "ABC_AddTarget: The target gate \"%s\" is not in the network.\n", names[i] ); return 0; }
Vec_PtrPush( mng->vNodes, pObj );
if ( values[i] < 0 || values[i] > 1 )
{ printf( "ABC_AddTarget: The value of gate \"%s\" is not 0 or 1.\n", names[i] ); return 0; }
Vec_IntPush( mng->vValues, values[i] );
}
mng->nog = nog;
return 1;
}
/**Function*************************************************************
Synopsis [Connect one box.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Io_ReadBlifNetworkConnectBoxesOneBox( Io_ReadBlif_t * p, Abc_Obj_t * pBox, stmm_table * tName2Model )
{
Vec_Ptr_t * pNames;
Abc_Ntk_t * pNtkModel;
Abc_Obj_t * pObj, * pNet;
char * pName = NULL, * pActual;
int i, Length, Start = -1;
// get the model for this box
pNames = (Vec_Ptr_t *)pBox->pData;
if ( !stmm_lookup( tName2Model, (char *)Vec_PtrEntry(pNames, 0), (char **)&pNtkModel ) )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Cannot find the model for subcircuit %s.", (char*)Vec_PtrEntry(pNames, 0) );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
// create the fanins of the box
Abc_NtkForEachPi( pNtkModel, pObj, i )
pObj->pCopy = NULL;
if ( Abc_NtkPiNum(pNtkModel) == 0 )
Start = 1;
else
{
Vec_PtrForEachEntryStart( char *, pNames, pName, i, 1 )
{
pActual = Io_ReadBlifCleanName(pName);
if ( pActual == NULL )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Cannot parse formal/actual name pair \"%s\".", pName );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
Length = pActual - pName - 1;
pName[Length] = 0;
// find the PI net with this name
pObj = Abc_NtkFindNet( pNtkModel, pName );
if ( pObj == NULL )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Cannot find formal input \"%s\" as an PI of model \"%s\".", pName, (char*)Vec_PtrEntry(pNames, 0) );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
// get the PI
pObj = Abc_ObjFanin0(pObj);
// quit if this is not a PI net
if ( !Abc_ObjIsPi(pObj) )
{
pName[Length] = '=';
Start = i;
break;
}
// remember the actual name in the net
if ( pObj->pCopy != NULL )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Formal input \"%s\" is used more than once.", pName );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
pObj->pCopy = (Abc_Obj_t *)pActual;
// quit if we processed all PIs
if ( i == Abc_NtkPiNum(pNtkModel) )
{
Start = i+1;
break;
}
}
}
// create the fanins of the box
Abc_NtkForEachPi( pNtkModel, pObj, i )
{
pActual = (char *)pObj->pCopy;
if ( pActual == NULL )
{
p->LineCur = (int)(ABC_PTRINT_T)pBox->pCopy;
sprintf( p->sError, "Formal input \"%s\" of model %s is not driven.", pName, (char*)Vec_PtrEntry(pNames, 0) );
Io_ReadBlifPrintErrorMessage( p );
return 1;
}
pNet = Abc_NtkFindOrCreateNet( pBox->pNtk, pActual );
Abc_ObjAddFanin( pBox, pNet );
}
/**Function*************************************************************
Synopsis [Adds a gate to the circuit.]
Description [The meaning of the parameters are:
type: the type of the gate to be added
name: the name of the gate to be added, name should be unique in a circuit.
nofi: number of fanins of the gate to be added;
fanins: the name array of fanins of the gate to be added.]
SideEffects []
SeeAlso []
***********************************************************************/
int ABC_AddGate( ABC_Manager mng, enum GateType type, char * name, int nofi, char ** fanins, int dc_attr )
{
Abc_Obj_t * pObj = NULL; // Suppress "might be used uninitialized"
Abc_Obj_t * pFanin;
char * pSop = NULL; // Suppress "might be used uninitialized"
char * pNewName;
int i;
// save the name in the local memory manager
pNewName = Mem_FlexEntryFetch( mng->pMmNames, strlen(name) + 1 );
strcpy( pNewName, name );
name = pNewName;
// consider different cases, create the node, and map the node into the name
switch( type )
{
case CSAT_BPI:
case CSAT_BPPI:
if ( nofi != 0 )
{ printf( "ABC_AddGate: The PI/PPI gate \"%s\" has fanins.\n", name ); return 0; }
// create the PI
pObj = Abc_NtkCreatePi( mng->pNtk );
stmm_insert( mng->tNode2Name, (char *)pObj, name );
break;
case CSAT_CONST:
case CSAT_BAND:
case CSAT_BNAND:
case CSAT_BOR:
case CSAT_BNOR:
case CSAT_BXOR:
case CSAT_BXNOR:
case CSAT_BINV:
case CSAT_BBUF:
// create the node
pObj = Abc_NtkCreateNode( mng->pNtk );
// create the fanins
for ( i = 0; i < nofi; i++ )
{
if ( !stmm_lookup( mng->tName2Node, fanins[i], (char **)&pFanin ) )
{ printf( "ABC_AddGate: The fanin gate \"%s\" is not in the network.\n", fanins[i] ); return 0; }
Abc_ObjAddFanin( pObj, pFanin );
}
// create the node function
switch( type )
{
case CSAT_CONST:
if ( nofi != 0 )
{ printf( "ABC_AddGate: The constant gate \"%s\" has fanins.\n", name ); return 0; }
pSop = Abc_SopCreateConst1( (Mem_Flex_t *)mng->pNtk->pManFunc );
break;
case CSAT_BAND:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The AND gate \"%s\" no fanins.\n", name ); return 0; }
pSop = Abc_SopCreateAnd( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi, NULL );
break;
case CSAT_BNAND:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The NAND gate \"%s\" no fanins.\n", name ); return 0; }
pSop = Abc_SopCreateNand( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi );
break;
case CSAT_BOR:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The OR gate \"%s\" no fanins.\n", name ); return 0; }
pSop = Abc_SopCreateOr( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi, NULL );
break;
case CSAT_BNOR:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The NOR gate \"%s\" no fanins.\n", name ); return 0; }
pSop = Abc_SopCreateNor( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi );
break;
case CSAT_BXOR:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The XOR gate \"%s\" no fanins.\n", name ); return 0; }
if ( nofi > 2 )
{ printf( "ABC_AddGate: The XOR gate \"%s\" has more than two fanins.\n", name ); return 0; }
pSop = Abc_SopCreateXor( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi );
break;
case CSAT_BXNOR:
if ( nofi < 1 )
{ printf( "ABC_AddGate: The XNOR gate \"%s\" no fanins.\n", name ); return 0; }
if ( nofi > 2 )
{ printf( "ABC_AddGate: The XNOR gate \"%s\" has more than two fanins.\n", name ); return 0; }
pSop = Abc_SopCreateNxor( (Mem_Flex_t *)mng->pNtk->pManFunc, nofi );
break;
case CSAT_BINV:
if ( nofi != 1 )
{ printf( "ABC_AddGate: The inverter gate \"%s\" does not have exactly one fanin.\n", name ); return 0; }
pSop = Abc_SopCreateInv( (Mem_Flex_t *)mng->pNtk->pManFunc );
break;
case CSAT_BBUF:
if ( nofi != 1 )
{ printf( "ABC_AddGate: The buffer gate \"%s\" does not have exactly one fanin.\n", name ); return 0; }
pSop = Abc_SopCreateBuf( (Mem_Flex_t *)mng->pNtk->pManFunc );
break;
default :
break;
}
Abc_ObjSetData( pObj, pSop );
break;
case CSAT_BPPO:
case CSAT_BPO:
if ( nofi != 1 )
{ printf( "ABC_AddGate: The PO/PPO gate \"%s\" does not have exactly one fanin.\n", name ); return 0; }
// create the PO
pObj = Abc_NtkCreatePo( mng->pNtk );
stmm_insert( mng->tNode2Name, (char *)pObj, name );
// connect to the PO fanin
if ( !stmm_lookup( mng->tName2Node, fanins[0], (char **)&pFanin ) )
{ printf( "ABC_AddGate: The fanin gate \"%s\" is not in the network.\n", fanins[0] ); return 0; }
Abc_ObjAddFanin( pObj, pFanin );
break;
default:
printf( "ABC_AddGate: Unknown gate type.\n" );
break;
}
// map the name into the node
if ( stmm_insert( mng->tName2Node, name, (char *)pObj ) )
{ printf( "ABC_AddGate: The same gate \"%s\" is added twice.\n", name ); return 0; }
return 1;
}
/**Function*************************************************************
Synopsis [Maps virtual latches into real latches.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Obj_t * Seq_NtkShareLatches_rec( Abc_Ntk_t * pNtk, Abc_Obj_t * pObj, Seq_Lat_t * pRing, int nLatch, stmm_table * tLatchMap )
{
Abc_Obj_t * pLatch, * pFanin;
Abc_InitType_t Init;
unsigned Key;
if ( nLatch == 0 )
return pObj;
assert( pRing->pLatch == NULL );
// get the latch on the previous level
pFanin = Seq_NtkShareLatches_rec( pNtk, pObj, Seq_LatNext(pRing), nLatch - 1, tLatchMap );
// get the initial state
Init = Seq_LatInit( pRing );
// check if the latch with this initial state exists
Key = Seq_NtkShareLatchesKey( pFanin, Init );
if ( stmm_lookup( tLatchMap, (char *)Key, (char **)&pLatch ) )
return pRing->pLatch = pLatch;
// does not exist
if ( Init != ABC_INIT_DC )
{
// check if the don't-care exists
Key = Seq_NtkShareLatchesKey( pFanin, ABC_INIT_DC );
if ( stmm_lookup( tLatchMap, (char *)Key, (char **)&pLatch ) ) // yes
{
// update the table
stmm_delete( tLatchMap, (char **)&Key, (char **)&pLatch );
Key = Seq_NtkShareLatchesKey( pFanin, Init );
stmm_insert( tLatchMap, (char *)Key, (char *)pLatch );
// change don't-care to the given value
pLatch->pData = (void *)Init;
return pRing->pLatch = pLatch;
}
// add the latch with this value
pLatch = Abc_NtkCreateLatch( pNtk );
pLatch->pData = (void *)Init;
Abc_ObjAddFanin( pLatch, pFanin );
// add it to the table
Key = Seq_NtkShareLatchesKey( pFanin, Init );
stmm_insert( tLatchMap, (char *)Key, (char *)pLatch );
return pRing->pLatch = pLatch;
}
// the init value is the don't-care
// check if care values exist
Key = Seq_NtkShareLatchesKey( pFanin, ABC_INIT_ZERO );
if ( stmm_lookup( tLatchMap, (char *)Key, (char **)&pLatch ) )
{
Seq_LatSetInit( pRing, ABC_INIT_ZERO );
return pRing->pLatch = pLatch;
}
Key = Seq_NtkShareLatchesKey( pFanin, ABC_INIT_ONE );
if ( stmm_lookup( tLatchMap, (char *)Key, (char **)&pLatch ) )
{
Seq_LatSetInit( pRing, ABC_INIT_ONE );
return pRing->pLatch = pLatch;
}
// create the don't-care latch
pLatch = Abc_NtkCreateLatch( pNtk );
pLatch->pData = (void *)ABC_INIT_DC;
Abc_ObjAddFanin( pLatch, pFanin );
// add it to the table
Key = Seq_NtkShareLatchesKey( pFanin, ABC_INIT_DC );
stmm_insert( tLatchMap, (char *)Key, (char *)pLatch );
return pRing->pLatch = pLatch;
}
