static int mmc_set_mclk(struct sunxi_mmc_host* mmchost, u32 clk_hz)
{
unsigned n, m, div, src, sclk_hz = 0;
unsigned rval;
MMCDBG("%s: mod_clk %d\n", __FUNCTION__, clk_hz);
if (clk_hz <= 4000000) { //400000
src = 0;
sclk_hz = 24000000;
} else {
src = 1;
sclk_hz = sunxi_clock_get_pll6()*2*1000000; /*use 2x pll-per0 clock */
}
div = (2 * sclk_hz + clk_hz) / (2 * clk_hz);
div = (div==0) ? 1 : div;
if (div > 128) {
m = 1;
n = 0;
MMCINFO("%s: source clock is too high, clk %d, src %d!!!\n",
__FUNCTION__, clk_hz, sclk_hz);
} else if (div > 64) {
n = 3;
m = div >> 3;
} else if (div > 32) {
int power_source_init(void)
{
int pll_cpux;
int cpu_vol;
int dcdc_vol;
int axp_exist = 0;
//PMU_SUPPLY_DCDC2 is for cpua
if(script_parser_fetch("power_sply", "dcdc2_vol", &dcdc_vol, 1))
{
cpu_vol = 900;
}
else
{
cpu_vol = dcdc_vol%10000;
}
axp_exist = axp_probe();
if(axp_exist)
{
axp_probe_factory_mode();
if(!axp_probe_power_supply_condition())
{
//PMU_SUPPLY_DCDC2 is for cpua
if(!axp_set_supply_status(0, PMU_SUPPLY_DCDC2, cpu_vol, -1))
{
tick_printf("PMU: dcdc2 %d\n", cpu_vol);
sunxi_clock_set_corepll(uboot_spare_head.boot_data.run_clock);
}
else
{
printf("axp_set_dcdc2 fail\n");
}
}
else
{
printf("axp_probe_power_supply_condition error\n");
}
}
else
{
printf("axp_probe error\n");
}
pll_cpux = sunxi_clock_get_corepll();
tick_printf("PMU: cpux %d Mhz,AXI=%d Mhz\n", pll_cpux,sunxi_clock_get_axi());
printf("PLL6=%d Mhz,AHB=%d Mhz, APB1=%d Mhz \n", sunxi_clock_get_pll6(),
sunxi_clock_get_ahb(),
sunxi_clock_get_apb());
if(axp_exist)
{
axp_set_charge_vol_limit();
axp_set_all_limit();
axp_set_hardware_poweron_vol();
axp_set_power_supply_output();
power_config_gpio_bias();
power_limit_init();
}
return 0;
}
int power_source_init(void)
{
int pll1;
int cpu_vol;
int dcdc_vol;
if(script_parser_fetch("power_sply", "dcdc2_vol", &dcdc_vol, 1))
{
cpu_vol = 900;
}
else
{
cpu_vol = dcdc_vol%10000;
}
if(axp_probe() > 0)
{
axp_probe_factory_mode();
if(!axp_probe_power_supply_condition())
{
//PMU_SUPPLY_DCDC2 is for cpua
if(!axp_set_supply_status(0, PMU_SUPPLY_DCDC2, cpu_vol, -1))
{
tick_printf("PMU: dcdc2 %d\n", cpu_vol);
sunxi_clock_set_corepll(uboot_spare_head.boot_data.run_clock, 0);
}
else
{
printf("axp_set_dcdc2 fail\n");
}
}
else
{
printf("axp_probe_power_supply_condition error\n");
}
}
else
{
printf("axp_probe error\n");
}
pll1 = sunxi_clock_get_corepll();
tick_printf("PMU: pll1 %d Mhz\n", pll1);
printf("AXI0=%d Mhz,PLL_PERIPH =%d Mhz AHB1=%d Mhz, APB1=%d Mhz \n",
sunxi_clock_get_axi(),
sunxi_clock_get_pll6(),
sunxi_clock_get_ahb(),
sunxi_clock_get_apb1());
axp_set_charge_vol_limit();
axp_set_all_limit();
axp_set_hardware_poweron_vol();
axp_set_power_supply_output();
power_config_gpio_bias();
power_limit_init();
// AXP and RTC use the same interrupt line, so disable RTC INT in uboot
disable_rtc_int();
return 0;
}
