__hdle OSAL_GPIO_Request(disp_gpio_set_t *gpio_list, __u32 group_count_max)
{
__hdle ret = 0;
struct gpio_config pin_cfg;
char pin_name[32];
__u32 config;
if(gpio_list == NULL)
return 0;
pin_cfg.gpio = gpio_list->gpio;
pin_cfg.mul_sel = gpio_list->mul_sel;
pin_cfg.pull = gpio_list->pull;
pin_cfg.drv_level = gpio_list->drv_level;
pin_cfg.data = gpio_list->data;
ret = gpio_request(pin_cfg.gpio, NULL);
if(0 != ret) {
__wrn("OSAL_GPIO_Request failed, gpio_name=%s, gpio=%d, ret=%d\n", gpio_list->gpio_name, gpio_list->gpio, ret);
return ret;
} else {
__inf("OSAL_GPIO_Request, gpio_name=%s, gpio=%d, ret=%d\n", gpio_list->gpio_name, gpio_list->gpio, ret);
}
ret = pin_cfg.gpio;
#if 1
if (!IS_AXP_PIN(pin_cfg.gpio)) {
/* valid pin of sunxi-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg.gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg.mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg.pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg.pull);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg.drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg.drv_level);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg.data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg.data);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
} else if (IS_AXP_PIN(pin_cfg.gpio)) {
/* valid pin of axp-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg.gpio, pin_name);
if (pin_cfg.data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg.data);
pin_config_set(AXP_PINCTRL, pin_name, config);
}
} else {
pr_warn("invalid pin [%d] from sys-config\n", pin_cfg.gpio);
}
#endif
return ret;
}
static int sunxi_pin_resource_req(struct platform_device *pdev)
{
script_item_u *pin_list;
int pin_count;
int pin_index;
pr_warn("device [%s] pin resource request enter\n", dev_name(&pdev->dev));
/* get pin sys_config info */
pin_count = script_get_pio_list("lcd0", &pin_list);
if (pin_count == 0) {
/* "lcd0" have no pin configuration */
return -EINVAL;
}
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
struct gpio_config *pin_cfg = &(pin_list[pin_index].gpio);
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
unsigned long config;
if (IS_AXP_PIN(pin_cfg->gpio)) {
/* valid pin of axp-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(AXP_PINCTRL, pin_name, config);
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set(AXP_PINCTRL, pin_name, config);
}
} else {
/* valid pin of sunxi-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg->pull);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg->drv_level);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
}
}
pr_debug("device [%s] pin resource request ok\n", dev_name(&pdev->dev));
return 0;
}
static int sunxi_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
__u32 temp;
#ifndef CONFIG_FPGA_V4_PLATFORM
int i;
__u32 ret = 0;
char pin_name[255];
__u32 config;
for(i = 0; i < pwm_pin_count[pwm->pwm]; i++) {
ret = gpio_request(pwm_cfg[pwm->pwm].list[i].gpio.gpio, NULL);
if(ret != 0) {
pr_warn("pwm gpio %d request failed!\n", pwm_cfg[pwm->pwm].list[i].gpio.gpio);
}
if(!IS_AXP_PIN(pwm_cfg[pwm->pwm].list[i].gpio.gpio)) {
sunxi_gpio_to_name(pwm_cfg[pwm->pwm].list[i].gpio.gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pwm_cfg[pwm->pwm].list[i].gpio.mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
else {
pr_warn("this is axp pin!\n");
}
gpio_free(pwm_cfg[pwm->pwm].list[i].gpio.gpio);
}
#endif
#if ((defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN9IW1P1))
temp = sunxi_pwm_read_reg(pwm->pwm * 0x10);
temp |= 1 << 4;
temp |= 1 << 6;
sunxi_pwm_write_reg(pwm->pwm * 0x10, temp);
#elif defined(CONFIG_ARCH_SUN8IW3P1) || defined(CONFIG_ARCH_SUN8IW5P1) || defined(CONFIG_ARCH_SUN8IW6P1) || defined(CONFIG_ARCH_SUN8IW9P1) || defined(CONFIG_ARCH_SUN8IW8P1)
temp = sunxi_pwm_read_reg(0);
if(pwm->pwm == 0) {
temp |= 1 << 4;
temp |= 1 << 6;
} else {
temp |= 1 << 19;
temp |= 1 << 21;
}
sunxi_pwm_write_reg(0, temp);
#endif
return 0;
}
void NAND_PIORequest(__u32 nand_index)
{
script_item_u *pin_list;
int pin_count;
int pin_index;
PRINT_LEVEL = NAND_Print_level();
/* get pin sys_config info */
if(nand_index == 0)
{
pin_count = script_get_pio_list("nand0_para", &pin_list);
NAND_Print_DBG("pin count:%d \n",pin_count);
}
else if(nand_index == 1)
pin_count = script_get_pio_list("nand1_para", &pin_list);
else
return ;
if (pin_count == 0) {
/* "lcd0" have no pin configuration */
printk("pin count 0\n");
return ;
}
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
struct gpio_config *pin_cfg = &(pin_list[pin_index].gpio);
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
unsigned long config;
/* valid pin of sunxi-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg->pull);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg->drv_level);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
}
*((volatile unsigned int *)0xf6000b08)= 0xa;
NAND_Print_DBG("nand:gpioc bias config:%x \n",*((volatile unsigned int *)0xf6000b08));
return ;
}
static __s32 camera_req_mclk_pin(__u32 csi_index)
{
#ifdef VFE_GPIO
char *csi_para[2] = {"csi0", "csi1"};
int req_status;
script_item_u item;
script_item_value_type_e type;
char pin_name[32];
__u32 config;
/* ��ȡgpio list */
type = script_get_item(csi_para[csi_index], "vip_csi_mck", &item);
if(SCIRPT_ITEM_VALUE_TYPE_PIO != type) {
camera_err("script_get_item return type err\n");
return -ECFGERR;
}
/* ����gpio */
req_status = gpio_request(item.gpio.gpio, NULL);
if(0 != req_status) {
camera_err("request gpio failed\n");
return -ENORMALPIN;
}
/* ����gpio */
sunxi_gpio_to_name(item.gpio.gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, item.gpio.mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (item.gpio.pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, item.gpio.pull);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (item.gpio.drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, item.gpio.drv_level);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (item.gpio.data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, item.gpio.data);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
/* �ͷ�gpio */
if(0 == req_status)
gpio_free(item.gpio.gpio);
return 0;
#else
return 0;
#endif
}
static int sunxi_daudio0_suspend(struct snd_soc_dai *cpu_dai)
{
u32 reg_val;
u32 pin_index = 0;
u32 config;
struct gpio_config *pin_daudio0_cfg;
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
pr_debug("[DAUDIO]Entered %s\n", __func__);
/*Global disable Digital Audio Interface*/
reg_val = sunxi_smc_readl(sunxi_daudio.regs + SUNXI_DAUDIOCTL);
reg_val &= ~SUNXI_DAUDIOCTL_GEN;
sunxi_smc_writel(reg_val, sunxi_daudio.regs + SUNXI_DAUDIOCTL);
daudioregsave();
if ((NULL == daudio_moduleclk) ||(IS_ERR(daudio_moduleclk))) {
pr_err("daudio_moduleclk handle is invalid, just return\n");
return -EFAULT;
} else {
/*release the module clock*/
clk_disable(daudio_moduleclk);
}
#if defined(CONFIG_ARCH_SUN8IW6) || defined(CONFIG_ARCH_SUN8IW8)
if ((NULL == daudio_pll2clk) ||(IS_ERR(daudio_pll2clk))) {
pr_err("daudio_pll2clk handle is invalid, just return\n");
return -EFAULT;
} else {
/*release the module clock*/
clk_disable(daudio_pll2clk);
}
if ((NULL == daudio_pllx8) ||(IS_ERR(daudio_pllx8))) {
pr_err("daudio_pllx8 handle is invalid, just return\n");
return -EFAULT;
} else {
/*release the module clock*/
clk_disable(daudio_pllx8);
}
#endif
devm_pinctrl_put(daudio_pinctrl);
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
pin_daudio0_cfg = &(pin_daudio0_list[pin_index].gpio);
/* valid pin of sunxi-pinctrl, config pin attributes individually.*/
sunxi_gpio_to_name(pin_daudio0_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, 7);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
return 0;
}
static int sunxi_pin_cfg_check(struct gpio_config *pin_cfg)
{
int fail_cnt = 0;
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
unsigned long config;
/* get gpio name */
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
/* check function config */
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, 0xFFFF);
pin_config_get(SUNXI_PINCTRL, pin_name, &config);
if (pin_cfg->mul_sel != SUNXI_PINCFG_UNPACK_VALUE(config)) {
fail_cnt++;
pr_warn("sunxi pin [%s] func config error, [%d != %ld]\n",
pin_name, pin_cfg->mul_sel, SUNXI_PINCFG_UNPACK_VALUE(config));
}
/* check pull config */
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, 0xFFFF);
pin_config_get(SUNXI_PINCTRL, pin_name, &config);
if (pin_cfg->pull != SUNXI_PINCFG_UNPACK_VALUE(config)) {
fail_cnt++;
pr_warn("sunxi pin [%s] pull config error, [%d != %ld]\n",
pin_name, pin_cfg->pull, SUNXI_PINCFG_UNPACK_VALUE(config));
}
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, 0xFFFF);
pin_config_get(SUNXI_PINCTRL, pin_name, &config);
if (pin_cfg->pull != SUNXI_PINCFG_UNPACK_VALUE(config)) {
fail_cnt++;
pr_warn("sunxi pin [%s] driver level config error, [%d != %ld]\n",
pin_name, pin_cfg->drv_level, SUNXI_PINCFG_UNPACK_VALUE(config));
}
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, 0xFFFF);
pin_config_get(SUNXI_PINCTRL, pin_name, &config);
if (pin_cfg->data != SUNXI_PINCFG_UNPACK_VALUE(config)) {
fail_cnt++;
pr_warn("sunxi pin [%s] data config error, [%d != %ld]\n",
pin_name, pin_cfg->drv_level, SUNXI_PINCFG_UNPACK_VALUE(config));
}
}
return fail_cnt;
}
int __sysfs_dump_mainkey(script_main_key_t *pmainkey, char *buf)
{
script_sub_key_t *psubkey = NULL;
int cnt = 0;
char gpio_name[8] = {0};
if(NULL == pmainkey || NULL == pmainkey->subkey || NULL == pmainkey->subkey_val)
return 0;
cnt += sprintf(buf + cnt, "++++++++++++++++++++++++++%s++++++++++++++++++++++++++\n", __func__);
cnt += sprintf(buf + cnt, " name: %s\n", pmainkey->name);
cnt += sprintf(buf + cnt, " sub_key: name type value\n");
psubkey = pmainkey->subkey;
while(psubkey) {
switch(psubkey->type) {
case SCIRPT_ITEM_VALUE_TYPE_INT:
cnt += sprintf(buf + cnt, " %-15s%-10s%d\n", psubkey->name,
ITEM_TYPE_TO_STR(psubkey->type), psubkey->value->val);
break;
case SCIRPT_ITEM_VALUE_TYPE_STR:
cnt += sprintf(buf + cnt, " %-15s%-10s\"%s\"\n", psubkey->name,
ITEM_TYPE_TO_STR(psubkey->type), psubkey->value->str);
break;
case SCIRPT_ITEM_VALUE_TYPE_PIO:
sunxi_gpio_to_name(psubkey->value->gpio.gpio, gpio_name);
cnt += sprintf(buf + cnt, " %-15s%-10s(gpio: %#x / %s, mul: %d, pull %d, drv %d, data %d)\n",
psubkey->name, ITEM_TYPE_TO_STR(psubkey->type),
psubkey->value->gpio.gpio, gpio_name,
psubkey->value->gpio.mul_sel,
psubkey->value->gpio.pull, psubkey->value->gpio.drv_level, psubkey->value->gpio.data);
break;
default:
cnt += sprintf(buf + cnt, " %-15sinvalid type!\n", psubkey->name);
break;
}
psubkey = psubkey->next;
}
cnt += sprintf(buf + cnt, "--------------------------%s--------------------------\n", __func__);
return cnt;
}
__s32 NAND_PIOFuncChange_REc(__u32 nand_index, __u32 en)
{
unsigned int ndfc_version;
script_item_u *pin_list;
int pin_count;
int pin_index;
ndfc_version = NAND_GetNdfcVersion();
if (ndfc_version == 1) {
printk("NAND_PIOFuncChange_EnDQScREc: invalid ndfc version!\n");
return 0;
}
/* get pin sys_config info */
if(nand_index == 0)
pin_count = script_get_pio_list("nand0", &pin_list);
else if(nand_index == 1)
pin_count = script_get_pio_list("nand1", &pin_list);
else {
pin_count = 0;
printk("NAND_PIOFuncChange_DQSc, wrong nand index %d\n", nand_index);
}
if (pin_count == 0) {
/* "lcd0" have no pin configuration */
return 0;
}
{
struct gpio_config *pin_cfg;
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
unsigned long config;
/* change pin func from CE2 to REc */
pin_index = 17;
if (pin_index > pin_count) {
printk("NAND_PIOFuncChange_EnREc: pin_index error, %d/%d\n", pin_index, pin_count);
return -1;
}
pin_cfg = &(pin_list[pin_index].gpio);
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
if (en) {
if ((config & 0xffff) == 0x3)
printk("REc has already been enabled!\n");
else if ((config & 0xffff) == 0x2){
config &= ~(0xffff);
config |= 0x3;
pin_config_set(SUNXI_PINCTRL, pin_name, config);
} else {
printk("NAND_PIOFuncChange_EnREc: wrong pin func status: %d %d\n", pin_index, (__u32)(config & 0xffff));
}
} else {
if ((config & 0xffff) == 0x2)
printk("REc has already been disenabled!\n");
else if ((config & 0xffff) == 0x3){
config &= ~(0xffff);
config |= 0x3;
pin_config_set(SUNXI_PINCTRL, pin_name, config);
} else {
printk("NAND_PIOFuncChange_EnREc: wrong pin func status: %d %d\n", pin_index, (__u32)(config & 0xffff));
}
}
}
return 0;
}
int os_gpio_set(struct vfe_gpio_cfg *gpio_list, __u32 group_count_max)
{
#ifdef VFE_GPIO
int ret = 0;
struct gpio_config pin_cfg;
char pin_name[32];
__u32 config;
if(gpio_list == NULL)
return 0;
if(gpio_list->gpio == GPIO_INDEX_INVALID)
return 0;
pin_cfg.gpio = gpio_list->gpio;
pin_cfg.mul_sel = gpio_list->mul_sel;
pin_cfg.pull = gpio_list->pull;
pin_cfg.drv_level = gpio_list->drv_level;
pin_cfg.data = gpio_list->data;
if (!IS_AXP_PIN(pin_cfg.gpio)) {
/* valid pin of sunxi-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg.gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg.mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg.pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg.pull);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg.drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg.drv_level);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg.data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg.data);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
}
} else if (IS_AXP_PIN(pin_cfg.gpio)) {
/* valid pin of axp-pinctrl,
* config pin attributes individually.
*/
sunxi_gpio_to_name(pin_cfg.gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg.mul_sel);
pin_config_set(AXP_PINCTRL, pin_name, config);
if (pin_cfg.data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg.data);
pin_config_set(AXP_PINCTRL, pin_name, config);
}
} else {
vfe_warn("invalid pin [%d] from sys-config\n", pin_cfg.gpio);
return -1;
}
return ret;
#else
return 0;
#endif
}
static int sunxi_arisc_pin_cfg(struct platform_device *pdev)
{
script_item_u script_val;
script_item_value_type_e type;
script_item_u *pin_list;
int pin_count = 0;
int pin_index = 0;
struct gpio_config *pin_cfg;
char pin_name[SUNXI_PIN_NAME_MAX_LEN];
unsigned long config;
ARISC_INF("device [%s] pin resource request enter\n", dev_name(&pdev->dev));
/*
* request arisc resources:
* p2wi/rsb gpio...
*/
/* get pin sys_config info */
#if defined CONFIG_ARCH_SUN8IW1P1
pin_count = script_get_pio_list ("s_p2twi0", &pin_list);
#elif (defined CONFIG_ARCH_SUN8IW3P1) || (defined CONFIG_ARCH_SUN8IW5P1) || (defined CONFIG_ARCH_SUN8IW6P1)
pin_count = script_get_pio_list ("s_rsb0", &pin_list);
#elif defined CONFIG_ARCH_SUN9IW1P1
pin_count = script_get_pio_list ("s_rsb0", &pin_list);
#else
#error "please select a platform\n"
#endif
if (pin_count == 0) {
/* "s_p2twi0" or "s_rsb0" have no pin configuration */
ARISC_WRN("arisc s_p2twi0/s_rsb0 have no pin configuration\n");
return -EINVAL;
}
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
pin_cfg = &(pin_list[pin_index].gpio);
/* valid pin of sunxi-pinctrl, config pin attributes individually.*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg->pull);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg->drv_level);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
}
/*
* request arisc resources:
* uart gpio...
*/
type = script_get_item("s_uart0", "s_uart_used", &script_val);
if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
ARISC_WRN("sys_config.fex have no arisc s_uart0 config!");
script_val.val = 0;
}
if (script_val.val) {
pin_count = script_get_pio_list ("s_uart0", &pin_list);
if (pin_count == 0) {
/* "s_uart0" have no pin configuration */
ARISC_WRN("arisc s_uart0 have no pin configuration\n");
return -EINVAL;
}
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
pin_cfg = &(pin_list[pin_index].gpio);
/* valid pin of sunxi-pinctrl, config pin attributes individually.*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg->pull);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg->drv_level);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
}
}
ARISC_INF("arisc uart debug config [%s] [%s] : %d\n", "s_uart0", "s_uart_used", script_val.val);
/*
* request arisc resources:
* jtag gpio...
*/
type = script_get_item("s_jtag0", "s_jtag_used", &script_val);
if (SCIRPT_ITEM_VALUE_TYPE_INT != type) {
ARISC_WRN("sys_config.fex have no arisc s_jtag0 config!");
script_val.val = 0;
}
if (script_val.val) {
pin_count = script_get_pio_list ("s_jtag0", &pin_list);
if (pin_count == 0) {
/* "s_jtag0" have no pin configuration */
ARISC_WRN("arisc s_jtag0 have no pin configuration\n");
return -EINVAL;
}
/* request pin individually */
for (pin_index = 0; pin_index < pin_count; pin_index++) {
pin_cfg = &(pin_list[pin_index].gpio);
/* valid pin of sunxi-pinctrl, config pin attributes individually.*/
sunxi_gpio_to_name(pin_cfg->gpio, pin_name);
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_FUNC, pin_cfg->mul_sel);
pin_config_set(SUNXI_PINCTRL, pin_name, config);
if (pin_cfg->pull != GPIO_PULL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_PUD, pin_cfg->pull);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->drv_level != GPIO_DRVLVL_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DRV, pin_cfg->drv_level);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
if (pin_cfg->data != GPIO_DATA_DEFAULT) {
config = SUNXI_PINCFG_PACK(SUNXI_PINCFG_TYPE_DAT, pin_cfg->data);
pin_config_set (SUNXI_PINCTRL, pin_name, config);
}
}
}
ARISC_INF("arisc jtag debug config [%s] [%s] : %d\n", "s_jtag0", "s_jtag_used", script_val.val);
ARISC_INF("device [%s] pin resource request ok\n", dev_name(&pdev->dev));
return 0;
}