int emacrx_dma_inblk(dma_addr_t buff_addr, __u32 len)
{
int ret;
#if defined CONFIG_ARCH_SUN4I || defined CONFIG_ARCH_SUN5I
struct dma_hw_conf emac_hwconf = {
.xfer_type = DMAXFER_D_SWORD_S_SWORD,
.hf_irq = SW_DMA_IRQ_FULL,
.cmbk = 0x03030303,
.dir = SW_DMA_RDEV,
.from = emacrx_dma.dma_addr,
.address_type = DMAADDRT_D_LN_S_IO,
.drqsrc_type = DRQ_TYPE_EMAC
};
ret = sw_dma_setflags(emacrx_dma.channel, SW_DMAF_AUTOSTART);
if (ret != 0)
return ret;
#else
dma_config_t emac_hwconf = {
.xfer_type = {
.src_data_width = DATA_WIDTH_32BIT,
.src_bst_len = DATA_BRST_4,
.dst_data_width = DATA_WIDTH_32BIT,
.dst_bst_len = DATA_BRST_4
},
.address_type = {
.src_addr_mode = DDMA_ADDR_IO,
.dst_addr_mode = DDMA_ADDR_LINEAR
},
.bconti_mode = false,
.src_drq_type = D_SRC_EMAC_RX,
.dst_drq_type = D_DST_SRAM,
.irq_spt = CHAN_IRQ_FD
};
#endif
ret = sunxi_dma_config(&emacrx_dma, &emac_hwconf, 0x03030303);
if (ret != 0)
return ret;
ret = sunxi_dma_enqueue(&emacrx_dma, buff_addr, len, 1);
if (ret != 0)
return ret;
ret = sunxi_dma_start(&emacrx_dma);
if (ret != 0)
return ret;
return 0;
}
int wemac_dma_config_start(__u8 rw, void * buff_addr, __u32 len)
{
int ret;
if(rw == 0){
struct dma_hw_conf emac_hwconf = {
.xfer_type = DMAXFER_D_SWORD_S_SWORD,
.hf_irq = SW_DMA_IRQ_FULL,
.cmbk = 0x03030303,
.dir = SW_DMA_RDEV,
.from = 0x01C0B04C,
.address_type = DMAADDRT_D_LN_S_IO,
.drqsrc_type = DRQ_TYPE_EMAC
};
ret = sw_dma_setflags(ch_rx, SW_DMAF_AUTOSTART);
if(ret!=0)
return ret;
ret = sw_dma_config(ch_rx, &emac_hwconf);
if(ret!=0)
return ret;
ret = emacrx_DMAEqueueBuf(ch_rx, buff_addr, len);
if(ret!=0)
return ret;
ret = sw_dma_ctrl(ch_rx, SW_DMAOP_START);
} else {
struct dma_hw_conf emac_hwconf = {
.xfer_type = DMAXFER_D_SWORD_S_SWORD,
.hf_irq = SW_DMA_IRQ_FULL,
.cmbk = 0x03030303,
.dir = SW_DMA_WDEV,
.to = 0x01C0B024,
.address_type = DMAADDRT_D_IO_S_LN,
.drqdst_type = DRQ_TYPE_EMAC
};
ret = sw_dma_setflags(ch_tx, SW_DMAF_AUTOSTART);
if(ret!=0)
return ret;
ret = sw_dma_config(ch_tx, &emac_hwconf);
if(ret!=0)
return ret;
ret = emactx_DMAEqueueBuf(ch_tx, buff_addr, len);
if(ret!=0)
return ret;
ret = sw_dma_ctrl(ch_tx, SW_DMAOP_START);
}
return 0;
}
__s32 emacrx_WaitDmaFinish(void)
{
unsigned long flags;
int i;
while(1){
local_irq_save(flags);
if (emacrx_dma_completed_flag){
local_irq_restore(flags);
break;
}
for(i=0;i<1000;i++);
local_irq_restore(flags);
}
return 0;
}
