uint8_t target_unlock_sequence(void) {
    uint32_t val;

    if (!swd_read_ap(MDM_IDR, &val)) {
        return 0;
    }
    // Read-only identification register that always reads as 0x001C_0000
    if (val != 0x001c0000) {
        return 0;
    }

    if (!swd_read_ap(MDM_CTRL, &val)) {
        return 0;
    }

    if (!swd_read_ap(MDM_STATUS, &val)) {
        return 0;
    }

    // flash in secured mode
    if (val & (1 << 2)) {
        target_set_state(RESET_HOLD);
        while (1) {
            if (!swd_write_ap(MDM_CTRL, 1)) {
                return 0;
            }

            if (!swd_read_ap(MDM_STATUS, &val)) {
                return 0;
            }

            if (val & 1) {
                break;
            }
        }

        while (1) {
            if (!swd_write_ap(MDM_CTRL, 0)) {
                return 0;
            }

            if (!swd_read_ap(MDM_STATUS, &val)) {
                return 0;
            }

            if (!swd_read_ap(MDM_CTRL, &val)) {
                return 0;
            }

            if (val == 0) {
                break;
            }
        }
    }

    return 1;
}
示例#2
0
uint8_t target_unlock_sequence(void)
{
    uint32_t val;

    // read the device ID
    if (!swd_read_ap(MDM_IDR, &val)) {
        return 0;
    }

    // verify the result
    if (val != MDM_ID) {
        return 0;
    }

    if (!swd_read_ap(MDM_STATUS, &val)) {
        return 0;
    }

    // flash in secured mode
    if (val & (1 << 2)) {
        // hold the device in reset
        swd_set_target_reset(1);

        // write the mass-erase enable bit
        if (!swd_write_ap(MDM_CTRL, 1)) {
            return 0;
        }

        while (1) {
            // wait until mass erase is started
            if (!swd_read_ap(MDM_STATUS, &val)) {
                return 0;
            }

            if (val & 1) {
                break;
            }
        }

        // mass erase in progress
        while (1) {
            // keep reading until procedure is complete
            if (!swd_read_ap(MDM_CTRL, &val)) {
                return 0;
            }

            if (val == 0) {
                break;
            }
        }
    }

    return 1;
}
示例#3
0
void swd_set_target_reset(uint8_t asserted)
{
    if (asserted) {
        swd_init_debug();
        //Set POWER->RESET on NRF to 1
        if(!swd_write_ap(AP_TAR, 0x40000000 + 0x544)) {
            return;
        }
        
		if(!swd_write_ap(AP_DRW, 1)){
            return;
        }
        //Hold RESET and SWCLK low for a minimum of 100us
        PIN_SWCLK_TCK_CLR();
        PIN_SWDIO_TMS_CLR();
        //os_dly_wait(1);
    } else {
        PIN_SWCLK_TCK_SET();
        PIN_SWDIO_TMS_SET();
    }
}
示例#4
0
//Erase NRF and blink every 50ms in the process
static void nrf_Emergency_Erase(){
    //make sure SWD is initialized
    if (!swd_init_debug()) {
		return;
	}
    
    blinkLED();    
    
    //Set NVMC->CONFIG on NRF to 2    
    if (!swd_write_ap(AP_TAR, 0x4001E000 + 0x504)) {
		return;
	}
    if (!swd_write_ap(AP_DRW, 2)) {
		return;
	}

    blinkLED();
    blinkLED();
   

    //Set NVMC->ERASEALL on NRF to 1 to start chip erase
    if (!swd_write_ap(AP_TAR, 0x4001E000 + 0x50C)) {
		return;
	}
    if (!swd_write_ap(AP_DRW, 1)) {
		return;
	}
    
    blinkLED();
    blinkLED();
    blinkLED();
    blinkLED();
    
    //Set NVMC->CONFIG on NRF to 0
    if (!swd_write_ap(AP_TAR, 0x4001E000 + 0x504)) {
		return;
	}
    if (!swd_write_ap(AP_DRW, 0)) {
		return;
	}
    
    blinkLED();
    blinkLED();

	//swd_set_target_state(RESET_PROGRAM);
	//target_flash_init(SystemCoreClock);
	//target_flash_program_page(0,(uint8_t *)nrfBlinkyApp,800);

}