static int uart_ns16550_init(struct device *dev) { ARG_UNUSED(dev); #ifdef CONFIG_UART_NS16550_PORT_0 sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_0_INT_MASK), INT_ENABLE_ARC_BIT_POS); #endif /* CONFIG_UART_NS16550_PORT_0 */ #ifdef CONFIG_UART_NS16550_PORT_1 sys_clear_bit((SCSS_REGISTER_BASE + UART_NS16550_PORT_1_INT_MASK), INT_ENABLE_ARC_BIT_POS); #endif /* CONFIG_UART_NS16550_PORT_1 */ return 0; }
static void dw_set_bit(uint32_t base_addr, uint32_t offset, uint32_t bit, uint8_t value) { if (!value) { sys_clear_bit(base_addr + offset, bit); } else { sys_set_bit(base_addr + offset, bit); } }
/** * @brief Enable SPI module operation. * @param dev Pointer to the device structure for the driver instance * @return None. */ static inline void spi_k64_start(struct device *dev) { struct spi_k64_config *info = dev->config->config_info; /* Allow module operation */ sys_clear_bit((info->regs + SPI_K64_REG_MCR), SPI_K64_MCR_HALT_BIT); }
static void set_channel_irq_state(int channel, int enable) { mem_addr_t addr = QUARK_SE_IPM_MASK; int bit = channel + QUARK_SE_IPM_MASK_START_BIT; if (enable) { sys_clear_bit(addr, bit); } else { sys_set_bit(addr, bit); } }
/** * @brief Resume SPI host controller operations. * @param dev Pointer to the device structure for the driver instance * @return DEV_OK if successful, another DEV_* code otherwise. */ static int spi_k64_resume(struct device *dev) { struct spi_k64_config *info = dev->config->config_info; DBG("spi_k64_resume: %p\n", dev); /* enable module */ sys_clear_bit((info->regs + SPI_K64_REG_MCR), SPI_K64_MCR_MDIS_BIT); irq_enable(info->irq); return DEV_OK; }