static int sparc32_dma_init1(SysBusDevice *dev)
{
DMAState *s = FROM_SYSBUS(DMAState, dev);
int reg_size;
sysbus_init_irq(dev, &s->irq);
reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
memory_region_init_io(&s->iomem, &dma_mem_ops, s, "dma", reg_size);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
return 0;
}
static int sun4c_intctl_init1(SysBusDevice *dev)
{
Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
unsigned int i;
memory_region_init_io(&s->iomem, &sun4c_intctl_mem_ops, s,
"intctl", INTCTL_SIZE);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
for (i = 0; i < MAX_PILS; i++) {
sysbus_init_irq(dev, &s->cpu_irqs[i]);
}
return 0;
}
static int esp_init1(SysBusDevice *dev)
{
ESPState *s = FROM_SYSBUS(ESPState, dev);
sysbus_init_irq(dev, &s->irq);
assert(s->it_shift != -1);
memory_region_init_io(&s->iomem, &esp_mem_ops, s,
"esp", ESP_REGS << s->it_shift);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info);
return scsi_bus_legacy_handle_cmdline(&s->bus);
}
static int sp804_init(SysBusDevice *dev)
{
sp804_state *s = FROM_SYSBUS(sp804_state, dev);
qemu_irq *qi;
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
sysbus_init_irq(dev, &s->irq);
s->timer[0] = arm_timer_init(s->freq0);
s->timer[1] = arm_timer_init(s->freq1);
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
return 0;
}
static int esp_init1(SysBusDevice *dev)
{
ESPState *s = FROM_SYSBUS(ESPState, dev);
int esp_io_memory;
sysbus_init_irq(dev, &s->irq);
assert(s->it_shift != -1);
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s);
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1);
scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, esp_command_complete);
return scsi_bus_legacy_handle_cmdline(&s->bus);
}
static int tusb6010_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
TUSBState *s = TUSB(dev);
s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
memory_region_init_io(&s->iomem[1], OBJECT(s), &tusb_async_ops, s,
"tusb-async", UINT32_MAX);
sysbus_init_mmio(sbd, &s->iomem[0]);
sysbus_init_mmio(sbd, &s->iomem[1]);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1);
s->musb = musb_init(dev, 1);
return 0;
}
static int xilinx_uartlite_init(SysBusDevice *dev)
{
struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
sysbus_init_irq(dev, &s->irq);
uart_update_status(s);
memory_region_init_io(&s->mmio, &uart_ops, s, "xlnx.xps-uartlite",
R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
s->chr = qemu_char_get_next_serial();
if (s->chr)
qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
return 0;
}
static int lm32_uart_init(SysBusDevice *dev)
{
LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, &uart_ops, s, "uart", R_MAX * 4);
sysbus_init_mmio(dev, &s->iomem);
s->chr = qemu_char_get_next_serial();
if (s->chr) {
qemu_chr_add_handlers(s->chr, &uart_handlers, s);
}
return 0;
}
static int xilinx_uartlite_init(SysBusDevice *dev)
{
XilinxUARTLite *s = XILINX_UARTLITE(dev);
sysbus_init_irq(dev, &s->irq);
uart_update_status(s);
memory_region_init_io(&s->mmio, OBJECT(s), &uart_ops, s,
TYPE_XILINX_UARTLITE, R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
s->chr = qemu_char_get_next_serial();
if (s->chr)
qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
return 0;
}
static int puv3_intc_init(SysBusDevice *dev)
{
PUV3INTCState *s = FROM_SYSBUS(PUV3INTCState, dev);
qdev_init_gpio_in(&s->busdev.qdev, puv3_intc_handler, PUV3_IRQS_NR);
sysbus_init_irq(&s->busdev, &s->parent_irq);
s->reg_ICMR = 0;
s->reg_ICPR = 0;
memory_region_init_io(&s->iomem, &puv3_intc_ops, s, "puv3_intc",
PUV3_REGS_OFFSET);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static int mipsnet_sysbus_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
MIPSnetState *s = MIPS_NET(dev);
memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s,
"mipsnet-io", 36);
sysbus_init_mmio(sbd, &s->io);
sysbus_init_irq(sbd, &s->irq);
s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
return 0;
}
static void ss_init(Object *Obj)
{
SlaveBootInt *s = SBI(Obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(Obj);
object_property_add_link(Obj, "stream-connected-sbi", TYPE_STREAM_SLAVE,
(Object **) &s->tx_dev,
qdev_prop_allow_set_link_before_realize,
OBJ_PROP_LINK_UNREF_ON_RELEASE,
NULL);
memory_region_init_io(&s->iomem, Obj, &ss_ops, s,
TYPE_SBI, R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
static int syborg_int_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
SyborgIntState *s = SYBORG_INT(dev);
sysbus_init_irq(dev, &s->parent_irq);
qdev_init_gpio_in(&dev->qdev, syborg_int_set_irq, s->num_irqs);
memory_region_init_io(&s->iomem, &syborg_int_ops, s,
"interrupt", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
s->flags = g_malloc0(s->num_irqs * sizeof(syborg_int_flags));
register_savevm_live(&dev->qdev, "syborg_int", -1, 1,
&savevm_syborg_int, s);
return 0;
}
static int smc91c111_init1(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
smc91c111_state *s = SMC91C111(dev);
memory_region_init_io(&s->mmio, OBJECT(s), &smc91c111_mem_ops, s,
"smc91c111-mmio", 16);
sysbus_init_mmio(sbd, &s->mmio);
sysbus_init_irq(sbd, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->id, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
/* ??? Save/restore. */
return 0;
}
static int sp805_init(SysBusDevice *dev, const unsigned char *id)
{
int iomemtype;
sp805_state *s = FROM_SYSBUS(sp805_state, dev);
s->id = id;
iomemtype = cpu_register_io_memory(sp805_readfn,
sp805_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&dev->qdev, sp805_set_irq, 8);
qdev_init_gpio_out(&dev->qdev, s->out, 8);
sp805_reset(s);
register_savevm(&dev->qdev, "sp805_watchdog", -1, 1, sp805_save, sp805_load, s);
return 0;
}
static void xlx_iom_realize(DeviceState *dev, Error **errp)
{
XilinxPIT *s = XILINX_IO_MODULE_PIT(dev);
unsigned int i;
s->prefix = object_get_canonical_path(OBJECT(dev));
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
RegisterInfo *r = &s->regs_info[i];
*r = (RegisterInfo) {
.data = (uint8_t *)&s->regs[i],
.data_size = sizeof(uint32_t),
.access = &pit_regs_info[i],
.debug = XILINX_IO_MODULE_PIT_ERR_DEBUG,
.prefix = s->prefix,
.opaque = s,
};
memory_region_init_io(&r->mem, OBJECT(dev), &iom_pit_ops, r,
r->access->name, 4);
memory_region_add_subregion(&s->iomem, i * 4, &r->mem);
}
if (s->cfg.use) {
s->bh = qemu_bh_new(pit_timer_hit, s);
s->ptimer = ptimer_init(s->bh);
ptimer_set_freq(s->ptimer, s->frequency);
/* IRQ out to pulse when present timer expires/reloads */
qdev_init_gpio_out(dev, &s->hit_out, 1);
/* IRQ in to enable pre-scalar mode. Routed from gpo1 */
qdev_init_gpio_in_named(dev, iom_pit_ps_config, "ps_config", 1);
/* hit_out of neighbouring PIT is received as hit_in */
qdev_init_gpio_in_named(dev, iom_pit_ps_hit_in, "ps_hit_in", 1);
}
}
static void xlx_iom_pit_init(Object *obj)
{
XilinxPIT *s = XILINX_IO_MODULE_PIT(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &iom_pit_ops, s,
TYPE_XILINX_IO_MODULE_PIT,
R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
static int xilinx_uartlite_init(SysBusDevice *dev)
{
struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
int uart_regs;
sysbus_init_irq(dev, &s->irq);
uart_update_status(s);
uart_regs = cpu_register_io_memory(uart_read, uart_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr)
qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
return 0;
}
static int xilinx_ethlite_init(SysBusDevice *dev)
{
struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev);
sysbus_init_irq(dev, &s->irq);
s->rxbuf = 0;
memory_region_init_io(&s->mmio, ð_ops, s, "xlnx.xps-ethernetlite",
R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
object_get_typename(OBJECT(dev)), dev->qdev.id, s);
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
return 0;
}
static int milkymist_uart_init(SysBusDevice *dev)
{
MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev);
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->regs_region, &uart_mmio_ops, s,
"milkymist-uart", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr) {
qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
}
return 0;
}
static int lance_init(SysBusDevice *dev)
{
SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
PCNetState *s = &d->state;
memory_region_init_io(&s->mmio, &lance_mem_ops, d, "lance-mmio", 4);
qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
sysbus_init_mmio(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
s->phys_mem_read = ledma_memory_read;
s->phys_mem_write = ledma_memory_write;
return pcnet_common_init(&dev->qdev, s, &net_lance_info);
}
static int lm32_timer_init(SysBusDevice *dev)
{
LM32TimerState *s = FROM_SYSBUS(typeof(*s), dev);
int timer_regs;
sysbus_init_irq(dev, &s->irq);
s->bh = qemu_bh_new(timer_hit, s);
s->ptimer = ptimer_init(s->bh);
ptimer_set_freq(s->ptimer, s->freq_hz);
timer_regs = cpu_register_io_memory(timer_read_fn, timer_write_fn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, timer_regs);
return 0;
}
static int xilinx_ethlite_init(SysBusDevice *dev)
{
struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev);
int regs;
sysbus_init_irq(dev, &s->irq);
s->rxbuf = 0;
regs = cpu_register_io_memory(eth_read, eth_write, s, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, regs);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf,
dev->qdev.info->name, dev->qdev.id, s);
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
return 0;
}
static int sp804_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
SP804State *s = SP804(dev);
qemu_irq *qi;
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
sysbus_init_irq(sbd, &s->irq);
s->timer[0] = arm_timer_init(s->freq0);
s->timer[1] = arm_timer_init(s->freq1);
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
memory_region_init_io(&s->iomem, OBJECT(s), &sp804_ops, s,
"sp804", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
vmstate_register(dev, -1, &vmstate_sp804, s);
return 0;
}
static int smc91c111_init1(SysBusDevice *dev)
{
smc91c111_state *s = FROM_SYSBUS(smc91c111_state, dev);
s->mmio_index = cpu_register_io_memory(smc91c111_readfn,
smc91c111_writefn, s);
sysbus_init_mmio(dev, 16, s->mmio_index);
sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
smc91c111_reset(s);
s->nic = qemu_new_nic(&net_smc91c111_info, &s->conf,
dev->qdev.info->name, dev->qdev.id, s);
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
/* ??? Save/restore. */
return 0;
}
static int lm32_uart_init(SysBusDevice *dev)
{
LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
int uart_regs;
sysbus_init_irq(dev, &s->irq);
uart_regs = cpu_register_io_memory(uart_read_fn, uart_write_fn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, uart_regs);
s->chr = qdev_init_chardev(&dev->qdev);
if (s->chr) {
qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
}
return 0;
}
static int etraxfs_ser_init(SysBusDevice *dev)
{
ETRAXSerial *s = ETRAX_SERIAL(dev);
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->mmio, OBJECT(s), &ser_ops, s,
"etraxfs-serial", R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
/* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
s->chr = qemu_char_get_next_serial();
if (s->chr) {
qemu_chr_add_handlers(s->chr,
serial_can_receive, serial_receive,
serial_event, s);
}
return 0;
}
static int lance_init(SysBusDevice *dev)
{
SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
PCNetState *s = &d->state;
s->mmio_index =
cpu_register_io_memory(lance_mem_read, lance_mem_write, d);
qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
sysbus_init_mmio(dev, 4, s->mmio_index);
sysbus_init_irq(dev, &s->irq);
s->phys_mem_read = ledma_memory_read;
s->phys_mem_write = ledma_memory_write;
return pcnet_common_init(&dev->qdev, s, &net_lance_info);
}
static int sp804_init(SysBusDevice *dev)
{
sp804_state *s = FROM_SYSBUS(sp804_state, dev);
qemu_irq *qi;
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
sysbus_init_irq(dev, &s->irq);
/* ??? The timers are actually configurable between 32kHz and 1MHz, but
we don't implement that. */
s->timer[0] = arm_timer_init(1000000);
s->timer[1] = arm_timer_init(1000000);
s->timer[0]->irq = qi[0];
s->timer[1]->irq = qi[1];
memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
sysbus_init_mmio_region(dev, &s->iomem);
vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
return 0;
}
static int sysbus_esp_init(SysBusDevice *dev)
{
SysBusESPState *sysbus = FROM_SYSBUS(SysBusESPState, dev);
ESPState *s = &sysbus->esp;
sysbus_init_irq(dev, &s->irq);
assert(sysbus->it_shift != -1);
s->chip_id = TCHI_FAS100A;
memory_region_init_io(&sysbus->iomem, &sysbus_esp_mem_ops, sysbus,
"esp", ESP_REGS << sysbus->it_shift);
sysbus_init_mmio(dev, &sysbus->iomem);
qdev_init_gpio_in(&dev->qdev, sysbus_esp_gpio_demux, 2);
scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info);
return scsi_bus_legacy_handle_cmdline(&s->bus);
}
static void ftgmac100_realize(DeviceState *dev, Error **errp)
{
Ftgmac100State *s = FTGMAC100(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
memory_region_init_io(&s->iomem, OBJECT(dev), &ftgmac100_ops, s,
TYPE_FTGMAC100, 0x2000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->conf.peers.ncs[0] = nd_table[0].netdev;
s->nic = qemu_new_nic(&net_ftgmac100_info, &s->conf,
object_get_typename(OBJECT(dev)), DEVICE(dev)->id,
s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
}
