/*! \brief Enable the USART system clock in SPI master mode.
*
* \param p_usart Pointer to Base address of the USART instance.
*
*/
void usart_spi_init(volatile avr32_usart_t *p_usart)
{
#if (defined(AVR32_USART0_ADDRESS))
if ((uint32_t)p_usart == AVR32_USART0_ADDRESS)
{
sysclk_enable_pba_module(SYSCLK_USART0);
}
#endif
#if (defined(AVR32_USART1_ADDRESS))
if ((uint32_t)p_usart == AVR32_USART1_ADDRESS)
{
#if UC3C
sysclk_enable_pbc_module(SYSCLK_USART1);
#else
sysclk_enable_pba_module(SYSCLK_USART1);
#endif
}
#endif
#if (defined(AVR32_USART2_ADDRESS))
if ((uint32_t)p_usart == AVR32_USART2_ADDRESS)
{
sysclk_enable_pba_module(SYSCLK_USART2);
}
#endif
#if (defined(AVR32_USART3_ADDRESS))
if ((uint32_t)p_usart == AVR32_USART3_ADDRESS)
{
sysclk_enable_pba_module(SYSCLK_USART3);
}
#endif
}
/**
* \brief Enable a peripheral's clock from its base address.
*
* Enables the clock to a peripheral, given its base address. If the peripheral
* has an associated clock on the HSB bus, this will be enabled also.
*
* \param module Pointer to the module's base address.
*/
void sysclk_enable_peripheral_clock(const volatile void *module)
{
switch ((uintptr_t)module) {
#if !SAM4LS
case AESA_ADDR:
sysclk_enable_hsb_module(SYSCLK_AESA_HSB);
break;
#endif
case IISC_ADDR:
sysclk_enable_pba_module(SYSCLK_IISC);
break;
case SPI_ADDR:
sysclk_enable_pba_module(SYSCLK_SPI);
break;
case TC0_ADDR:
sysclk_enable_pba_module(SYSCLK_TC0);
sysclk_enable_pba_divmask(PBA_DIVMASK_TIMER_CLOCK2
| PBA_DIVMASK_TIMER_CLOCK3
| PBA_DIVMASK_TIMER_CLOCK4
| PBA_DIVMASK_TIMER_CLOCK5
);
break;
case TC1_ADDR:
sysclk_enable_pba_module(SYSCLK_TC1);
sysclk_enable_pba_divmask(PBA_DIVMASK_TIMER_CLOCK2
| PBA_DIVMASK_TIMER_CLOCK3
| PBA_DIVMASK_TIMER_CLOCK4
| PBA_DIVMASK_TIMER_CLOCK5
);
break;
case TWIM0_ADDR:
sysclk_enable_pba_module(SYSCLK_TWIM0);
break;
case TWIS0_ADDR:
sysclk_enable_pba_module(SYSCLK_TWIS0);
break;
case TWIM1_ADDR:
sysclk_enable_pba_module(SYSCLK_TWIM1);
break;
case TWIS1_ADDR:
sysclk_enable_pba_module(SYSCLK_TWIS1);
break;
case USART0_ADDR:
sysclk_enable_pba_module(SYSCLK_USART0);
sysclk_enable_pba_divmask(PBA_DIVMASK_CLK_USART);
break;
case USART1_ADDR:
sysclk_enable_pba_module(SYSCLK_USART1);
sysclk_enable_pba_divmask(PBA_DIVMASK_CLK_USART);
break;
case USART2_ADDR:
sysclk_enable_pba_module(SYSCLK_USART2);
sysclk_enable_pba_divmask(PBA_DIVMASK_CLK_USART);
break;
case USART3_ADDR:
sysclk_enable_pba_module(SYSCLK_USART3);
sysclk_enable_pba_divmask(PBA_DIVMASK_CLK_USART);
break;
case ADCIFE_ADDR:
sysclk_enable_pba_module(SYSCLK_ADCIFE);
break;
case DACC_ADDR:
sysclk_enable_pba_module(SYSCLK_DACC);
break;
case ACIFC_ADDR:
sysclk_enable_pba_module(SYSCLK_ACIFC);
break;
case GLOC_ADDR:
sysclk_enable_pba_module(SYSCLK_GLOC);
break;
case ABDACB_ADDR:
sysclk_enable_pba_module(SYSCLK_ABDACB);
break;
case TRNG_ADDR:
sysclk_enable_pba_module(SYSCLK_TRNG);
break;
case PARC_ADDR:
sysclk_enable_pba_module(SYSCLK_PARC);
break;
case CATB_ADDR:
sysclk_enable_pba_module(SYSCLK_CATB);
break;
case TWIM2_ADDR:
sysclk_enable_pba_module(SYSCLK_TWIM2);
break;
case TWIM3_ADDR:
sysclk_enable_pba_module(SYSCLK_TWIM3);
break;
#if !SAM4LS
case LCDCA_ADDR:
sysclk_enable_pba_module(SYSCLK_LCDCA);
break;
#endif
case HFLASHC_ADDR:
sysclk_enable_hsb_module(SYSCLK_HFLASHC_DATA);
sysclk_enable_pbb_module(SYSCLK_HFLASHC_REGS);
break;
case HCACHE_ADDR:
sysclk_enable_hsb_module(SYSCLK_HRAMC1_DATA);
sysclk_enable_pbb_module(SYSCLK_HRAMC1_REGS);
break;
case HMATRIX_ADDR:
sysclk_enable_pbb_module(SYSCLK_HMATRIX);
break;
case PDCA_ADDR:
sysclk_enable_hsb_module(SYSCLK_PDCA_HSB);
sysclk_enable_pbb_module(SYSCLK_PDCA_PB);
break;
case CRCCU_ADDR:
sysclk_enable_hsb_module(SYSCLK_CRCCU_DATA);
sysclk_enable_pbb_module(SYSCLK_CRCCU_REGS);
break;
case USBC_ADDR:
sysclk_enable_hsb_module(SYSCLK_USBC_DATA);
sysclk_enable_pbb_module(SYSCLK_USBC_REGS);
break;
case PEVC_ADDR:
sysclk_enable_pbb_module(SYSCLK_PEVC);
break;
case PM_ADDR:
sysclk_enable_pbc_module(SYSCLK_PM);
break;
case CHIPID_ADDR:
sysclk_enable_pbc_module(SYSCLK_CHIPID);
break;
case SCIF_ADDR:
sysclk_enable_pbc_module(SYSCLK_SCIF);
break;
case FREQM_ADDR:
sysclk_enable_pbc_module(SYSCLK_FREQM);
break;
case GPIO_ADDR:
sysclk_enable_pbc_module(SYSCLK_GPIO);
break;
case BPM_ADDR:
sysclk_enable_pbd_module(SYSCLK_BPM);
break;
case BSCIF_ADDR:
sysclk_enable_pbd_module(SYSCLK_BSCIF);
break;
case AST_ADDR:
sysclk_enable_pbd_module(SYSCLK_AST);
break;
case WDT_ADDR:
sysclk_enable_pbd_module(SYSCLK_WDT);
break;
case EIC_ADDR:
sysclk_enable_pbd_module(SYSCLK_EIC);
break;
case PICOUART_ADDR:
sysclk_enable_pbd_module(SYSCLK_PICOUART);
break;
default:
Assert(false);
return;
}
}
