void oaic_syscon_attach(struct device *parent, struct device *self, void *aux) { struct oaic_syscon_softc *ssc = (struct oaic_syscon_softc *)self; struct aic6250_softc *sc = (struct aic6250_softc *)self; struct confargs *ca = aux; bus_space_handle_t ioh; int intsrc; if (bus_space_map(ca->ca_iot, ca->ca_paddr, AIC_NREG << 2, 0, &ioh) != 0) { printf(": can't map registers\n"); return; } ssc->sc_iot = ca->ca_iot; ssc->sc_ioh = ioh; /* * Do NOT ask any question about this. */ *(volatile uint32_t *)0xfff840c0 = 0x6e; /* * According to the hardware manual (chapter 10 ``Programming the * Small Computer System Interface'', page 10-2), the ``Clock * Frequency Mode'' bit in control register #1 must be clear. This * hints the AIC6250 runs at 10MHz. */ sc->sc_freq = 10; sc->sc_initiator = 7; /* port A is an output port, single-ended mode */ sc->sc_cr0 = AIC_CR0_EN_PORT_A; /* port B used as the upper 8 bits of the 16-bit DMA path */ sc->sc_cr1 = AIC_CR1_ENABLE_16BIT_MEM_BUS; sc->sc_read = oaic_read; sc->sc_write = oaic_write; #if 0 sc->sc_dma_start = oaic_dmastart; sc->sc_dma_done = oaic_dmadone; #endif aic6250_attach(sc); ssc->sc_ih.ih_fn = (int(*)(void *))aic6250_intr; ssc->sc_ih.ih_arg = sc; ssc->sc_ih.ih_flags = 0; ssc->sc_ih.ih_ipl = IPL_BIO; intsrc = INTSRC_SCSI1; sysconintr_establish(intsrc, &ssc->sc_ih, self->dv_xname); }
void oosiop_syscon_attach(struct device *parent, struct device *self, void *aux) { struct oosiop_syscon_softc *ssc = (struct oosiop_syscon_softc *)self; struct oosiop_softc *sc = (struct oosiop_softc *)self; struct confargs *ca = aux; bus_space_handle_t ioh; int intsrc; if (bus_space_map(ca->ca_iot, ca->ca_paddr, OOSIOP_NREGS, 0, &ioh) != 0) { printf(": can't map registers\n"); return; } sc->sc_bst = ca->ca_iot; sc->sc_bsh = ioh; sc->sc_dmat = 0; /* no real use of tag yet */ sc->sc_freq = 33333333; /* XXX 25MHz models? */ sc->sc_chip = OOSIOP_700; sc->sc_id = 7; /* XXX */ sc->sc_scntl0 = OOSIOP_SCNTL0_EPC | OOSIOP_SCNTL0_EPG; sc->sc_dmode = OOSIOP_DMODE_BL_4; sc->sc_dwt = 0x4f; /* maximum DMA timeout allowable */ sc->sc_ctest7 = OOSIOP_CTEST7_DC; oosiop_attach(sc); ssc->sc_ih.ih_fn = (int(*)(void *))oosiop_intr; ssc->sc_ih.ih_arg = sc; ssc->sc_ih.ih_flags = 0; ssc->sc_ih.ih_ipl = IPL_BIO; intsrc = ca->ca_paddr == AV530_SCSI1 ? INTSRC_SCSI1 : INTSRC_SCSI2; sysconintr_establish(intsrc, &ssc->sc_ih, self->dv_xname); }
void dartattach(struct device *parent, struct device *self, void *aux) { struct dartsoftc *sc = (struct dartsoftc *)self; struct confargs *ca = aux; bus_space_handle_t ioh; if (ca->ca_ipl < 0) ca->ca_ipl = IPL_TTY; sc->sc_iot = ca->ca_iot; if (bus_space_map(sc->sc_iot, ca->ca_paddr, DART_SIZE, 0, &ioh) != 0) { printf(": can't map registers!\n"); return; } sc->sc_ioh = ioh; /* save standard initialization */ sc->sc_sv_reg.sv_mr1[A_PORT] = PARDIS | RXRTS | CL8; sc->sc_sv_reg.sv_mr2[A_PORT] = /* TXCTS | */ SB1; sc->sc_sv_reg.sv_csr[A_PORT] = BD9600; sc->sc_sv_reg.sv_cr[A_PORT] = TXEN | RXEN; sc->sc_sv_reg.sv_mr1[B_PORT] = PARDIS | RXRTS | CL8; sc->sc_sv_reg.sv_mr2[B_PORT] = /* TXCTS | */ SB1; sc->sc_sv_reg.sv_csr[B_PORT] = BD9600; sc->sc_sv_reg.sv_cr[B_PORT] = TXEN | RXEN; /* Start out with Tx and RX interrupts disabled */ /* Enable input port change interrupt */ sc->sc_sv_reg.sv_imr = IIPCHG; /* * Although we are still running using the BUG routines, * this device will be elected as the console after * autoconf. * We do not even test since we know we are an MVME188 and * console is always on the first port. */ printf(": console"); /* reset port a */ dart_write(sc, DART_CRA, RXRESET | TXDIS | RXDIS); DELAY_CR; dart_write(sc, DART_CRA, TXRESET | TXDIS | RXDIS); DELAY_CR; dart_write(sc, DART_CRA, ERRRESET | TXDIS | RXDIS); DELAY_CR; dart_write(sc, DART_CRA, BRKINTRESET | TXDIS | RXDIS); DELAY_CR; dart_write(sc, DART_CRA, MRRESET | TXDIS | RXDIS); DELAY_CR; /* reset port b */ dart_write(sc, DART_CRB, RXRESET | TXDIS | RXDIS); DELAY_CR; dart_write(sc, DART_CRB, TXRESET | TXDIS | RXDIS); DELAY_CR; dart_write(sc, DART_CRB, ERRRESET | TXDIS | RXDIS); DELAY_CR; dart_write(sc, DART_CRB, BRKINTRESET | TXDIS | RXDIS); DELAY_CR; dart_write(sc, DART_CRB, MRRESET | TXDIS | RXDIS); DELAY_CR; /* initialize ports */ dart_write(sc, DART_MR1A, sc->sc_sv_reg.sv_mr1[A_PORT]); dart_write(sc, DART_MR2A, sc->sc_sv_reg.sv_mr2[A_PORT]); dart_write(sc, DART_CSRA, sc->sc_sv_reg.sv_csr[A_PORT]); dart_write(sc, DART_CRA, sc->sc_sv_reg.sv_cr[A_PORT]); dart_write(sc, DART_MR1B, sc->sc_sv_reg.sv_mr1[B_PORT]); dart_write(sc, DART_MR2B, sc->sc_sv_reg.sv_mr2[B_PORT]); dart_write(sc, DART_CSRB, sc->sc_sv_reg.sv_csr[B_PORT]); dart_write(sc, DART_CRB, sc->sc_sv_reg.sv_cr[B_PORT]); /* initialize common register of a DUART */ dart_write(sc, DART_OPRS, OPDTRA | OPRTSA | OPDTRB | OPRTSB); dart_write(sc, DART_CTUR, SLCTIM >> 8); dart_write(sc, DART_CTLR, SLCTIM & 0xff); dart_write(sc, DART_ACR, BDSET2 | CCLK16 | IPDCDIB | IPDCDIA); dart_write(sc, DART_IMR, sc->sc_sv_reg.sv_imr); dart_write(sc, DART_OPCR, OPSET); dart_write(sc, DART_IVR, SYSCON_VECT + SYSCV_SCC); /* enable interrupts */ sc->sc_ih.ih_fn = dartintr; sc->sc_ih.ih_arg = sc; sc->sc_ih.ih_wantframe = 0; sc->sc_ih.ih_ipl = ca->ca_ipl; sysconintr_establish(SYSCV_SCC, &sc->sc_ih, self->dv_xname); printf("\n"); }