void pwdog_attach(device_t parent, device_t self, void *aux) { struct pwdog_softc *sc = device_private(self); struct pci_attach_args *const pa = (struct pci_attach_args *)aux; pcireg_t memtype; memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START); if (pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_iosize)) { aprint_error("\n"); aprint_error_dev(self, "PCI %s region not found\n", memtype == PCI_MAPREG_TYPE_IO ? "I/O" : "memory"); return; } printf("\n"); sc->sc_dev = self; pmf_device_register(self, pwdog_suspend, pwdog_resume); bus_space_write_1(sc->sc_iot, sc->sc_ioh, PWDOG_DISABLE, 0); sc->sc_smw.smw_name = device_xname(self); sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = pwdog_setmode; sc->sc_smw.smw_tickle = pwdog_tickle; sc->sc_smw.smw_period = PWDOG_MAX_PERIOD; if (sysmon_wdog_register(&sc->sc_smw)) aprint_error_dev(self, "couldn't register with sysmon\n"); else sc->sc_smw_valid = true; }
static void sbwdog_attach(device_t parent, device_t self, void *aux) { struct sbwdog_softc *sc = device_private(self); struct sbscd_attach_args *sa = aux; sc->sc_dev = self; sc->sc_wdog_period = SBWDOG_DEFAULT_PERIOD; sc->sc_addr = MIPS_PHYS_TO_KSEG1(sa->sa_base + sa->sa_locs.sa_offset); aprint_normal(": %d second period\n", sc->sc_wdog_period); sc->sc_smw.smw_name = device_xname(sc->sc_dev); sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = sbwdog_setmode; sc->sc_smw.smw_tickle = sbwdog_tickle; sc->sc_smw.smw_period = sc->sc_wdog_period; if (sysmon_wdog_register(&sc->sc_smw) != 0) aprint_error_dev(self, "unable to register with sysmon\n"); if (sa->sa_locs.sa_intr[0] != SBOBIOCF_INTR_DEFAULT) cpu_intr_establish(sa->sa_locs.sa_intr[0], IPL_HIGH, sbwdog_intr, sc); }
/* ARGSUSED */ static void mvsoctmr_attach(device_t parent, device_t self, void *aux) { struct mvsoctmr_softc *sc = device_private(self); struct marvell_attach_args *mva = aux; uint32_t rstoutn; aprint_naive("\n"); aprint_normal(": Marvell SoC Timer\n"); if (mvsoctmr_sc == NULL) mvsoctmr_sc = sc; sc->sc_dev = self; sc->sc_iot = mva->mva_iot; if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset, mva->mva_size, &sc->sc_ioh)) panic("%s: Cannot map registers", device_xname(self)); sc->sc_irq = mva->mva_irq; switch (mva->mva_model) { case MARVELL_ARMADAXP_MV78130: case MARVELL_ARMADAXP_MV78160: case MARVELL_ARMADAXP_MV78230: case MARVELL_ARMADAXP_MV78260: case MARVELL_ARMADAXP_MV78460: sc->sc_flags = TMR_FLAGS_ARMADAXP; break; } mvsoctmr_timecounter.tc_name = device_xname(self); mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, 1, 1); /* * stop watchdog timer, enable watchdog timer resets */ mvsoctmr_cntl(sc, MVSOCTMR_WATCHDOG, 0xffffffff, 0, 0); write_mlmbreg(MVSOC_MLMB_MLMBICR, ~(1<<MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ)); rstoutn = read_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR); write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, rstoutn | MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN); #ifdef DDB db_trap_callback = mvsoctmr_wdog_ddb_trap; #endif sc->sc_wdog.smw_name = device_xname(self); sc->sc_wdog.smw_cookie = sc; sc->sc_wdog.smw_setmode = mvsoctmr_wdog_setmode; sc->sc_wdog.smw_tickle = mvsoctmr_wdog_tickle; sc->sc_wdog.smw_period = MVSOC_WDOG_MAX_PERIOD; if (sysmon_wdog_register(&sc->sc_wdog) != 0) aprint_error_dev(self, "unable to register watchdog with sysmon\n"); }
static void geode_wdog_attach(device_t parent, device_t self, void *aux) { struct geode_wdog_softc *sc = device_private(self); uint8_t wdsts; aprint_naive(": Watchdog Timer\n"); aprint_normal(": AMD Geode SC1100 Watchdog Timer\n"); /* * Hook up the watchdog timer. */ sc->sc_gcb_dev = device_private(parent); sc->sc_smw.smw_name = device_xname(self); sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = geode_wdog_setmode; sc->sc_smw.smw_tickle = geode_wdog_tickle; sc->sc_smw.smw_period = 32; /* * Determine cause of the last reset, and issue a warning if it * was due to watchdog expiry. */ wdsts = bus_space_read_1(sc->sc_gcb_dev->sc_iot, sc->sc_gcb_dev->sc_ioh, SC1100_GCB_WDSTS); GEODE_DPRINTF(("%s: status %#02" PRIx8 "\n", device_xname(self), wdsts)); if (wdsts & SC1100_WDSTS_WDRST) aprint_error( "%s: WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n", device_xname(self)); /* reset WDOVF by writing 1 to it */ bus_space_write_1(sc->sc_gcb_dev->sc_iot, sc->sc_gcb_dev->sc_ioh, SC1100_GCB_WDSTS, wdsts & SC1100_WDSTS_WDOVF); if (sysmon_wdog_register(&sc->sc_smw) != 0) aprint_error("%s: unable to register watchdog with sysmon\n", device_xname(self)); /* cancel any pending countdown */ geode_wdog_disable(sc); attached = 1; }
void pldwdog_attach(device_t parent, device_t self, void *aux) { struct pldwdog_softc *sc = device_private(self); struct ebus_attach_args *ea = aux; printf("\n"); sc->sc_dev = self; sc->sc_btag = ea->ea_bustag; if (ea->ea_nreg < 1) { printf(": no registers??\n"); return; } if (ea->ea_nvaddr) sparc_promaddr_to_handle(sc->sc_btag, ea->ea_vaddr[0], &sc->sc_bh); else if (bus_space_map(sc->sc_btag, EBUS_ADDR_FROM_REG(&ea->ea_reg[0]), ea->ea_reg[0].size, 0, &sc->sc_bh) != 0) { printf(": can't map register space\n"); return; } sc->sc_wdog_period = PLD_WDOG_PERIOD_DEFAULT; sc->sc_smw.smw_name = device_xname(sc->sc_dev); sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = pldwdog_setmode; sc->sc_smw.smw_tickle = pldwdog_tickle; sc->sc_smw.smw_period = sc->sc_wdog_period; if (sysmon_wdog_register(&sc->sc_smw) != 0) aprint_error_dev(sc->sc_dev, "unable to register with sysmon\n"); /* pldwdog_regs(sc); */ #if 0 bus_intr_establish(ea->ea_bustag, ea->ea_intr[0], IPL_TTY, pldwdog_intr, sc); #endif }
static void sbwdog_attach(struct device *parent, struct device *self, void *aux) { struct sbwdog_softc *sc = (void *)self; struct sbscd_attach_args *sa = aux; sc->sc_wdog_period = SBWDOG_DEFAULT_PERIOD; sc->sc_addr = MIPS_PHYS_TO_KSEG1(sa->sa_base + sa->sa_locs.sa_offset); printf(": %d second period\n", sc->sc_wdog_period); sc->sc_smw.smw_name = sc->sc_dev.dv_xname; sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = sbwdog_setmode; sc->sc_smw.smw_tickle = sbwdog_tickle; sc->sc_smw.smw_period = sc->sc_wdog_period; if (sysmon_wdog_register(&sc->sc_smw) != 0) printf("%s: unable to register with sysmon\n", sc->sc_dev.dv_xname); }
static void as3722_attach(device_t parent, device_t self, void *aux) { struct as3722_softc * const sc = device_private(self); struct i2c_attach_args *ia = aux; int error; sc->sc_dev = self; sc->sc_i2c = ia->ia_tag; sc->sc_addr = ia->ia_addr; aprint_naive("\n"); aprint_normal(": AMS AS3822\n"); iic_acquire_bus(sc->sc_i2c, I2C_F_POLL); error = as3722_write(sc, AS3722_GPIO0_CTRL_REG, __SHIFTIN(AS3722_GPIO0_CTRL_IOSF_GPIO, AS3722_GPIO0_CTRL_IOSF) | __SHIFTIN(AS3722_GPIO0_CTRL_MODE_PULLDOWN, AS3722_GPIO0_CTRL_MODE), I2C_F_POLL); error += as3722_set_clear(sc, AS3722_WATCHDOG_CTRL_REG, __SHIFTIN(1, AS3722_WATCHDOG_CTRL_MODE), 0, I2C_F_POLL); iic_release_bus(sc->sc_i2c, I2C_F_POLL); if (error) aprint_error_dev(self, "couldn't setup watchdog\n"); sc->sc_smw.smw_name = device_xname(self); sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = as3722_wdt_setmode; sc->sc_smw.smw_tickle = as3722_wdt_tickle; sc->sc_smw.smw_period = AS3722_WATCHDOG_DEFAULT_PERIOD; aprint_normal_dev(self, "default watchdog period is %u seconds\n", sc->sc_smw.smw_period); if (sysmon_wdog_register(&sc->sc_smw) != 0) aprint_error_dev(self, "couldn't register with sysmon\n"); }
static void wdog_attach(struct device *parent, struct device *self, void *aux) { struct wdog_softc *sc = (void *)self; unsigned int processor_freq; if (board_info_get("processor-frequency", &processor_freq, sizeof(processor_freq)) == -1) processor_freq = 200 * 1000 * 1000; /* assume 200MHz */ sc->sc_wdog_period = (2LL << 29) / processor_freq; printf(": %d second period\n", sc->sc_wdog_period); sc->sc_smw.smw_name = sc->sc_dev.dv_xname; sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = wdog_setmode; sc->sc_smw.smw_tickle = wdog_tickle; sc->sc_smw.smw_period = sc->sc_wdog_period; if (sysmon_wdog_register(&sc->sc_smw) != 0) printf("%s: unable to register with sysmon\n", sc->sc_dev.dv_xname); }
static void wdog_attach(device_t parent, device_t self, void *aux) { struct wdog_softc * const sc = device_private(self); unsigned int processor_freq; prop_number_t freq; freq = prop_dictionary_get(board_properties, "processor-frequency"); KASSERT(freq != NULL); processor_freq = (unsigned int) prop_number_integer_value(freq); sc->sc_wdog_period = (2LL << 29) / processor_freq; aprint_normal(": %d second period\n", sc->sc_wdog_period); sc->sc_dev = self; sc->sc_smw.smw_name = device_xname(self); sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = wdog_setmode; sc->sc_smw.smw_tickle = wdog_tickle; sc->sc_smw.smw_period = sc->sc_wdog_period; if (sysmon_wdog_register(&sc->sc_smw) != 0) aprint_error_dev(self, "unable to register with sysmon\n"); }
static void itesio_isa_attach(device_t parent, device_t self, void *aux) { struct itesio_softc *sc = device_private(self); struct isa_attach_args *ia = aux; int i; uint8_t cr; sc->sc_iot = ia->ia_iot; if (bus_space_map(sc->sc_iot, ia->ia_io[0].ir_addr, 2, 0, &sc->sc_ioh)) { aprint_error(": can't map i/o space\n"); return; } aprint_naive("\n"); /* * Enter to the Super I/O MB PNP mode. */ itesio_enter(sc->sc_iot, sc->sc_ioh); /* * Get info from the Super I/O Global Configuration Registers: * Chip IDs and Device Revision. */ sc->sc_chipid = (itesio_readreg(sc->sc_iot, sc->sc_ioh, ITESIO_CHIPID1) << 8); sc->sc_chipid |= itesio_readreg(sc->sc_iot, sc->sc_ioh, ITESIO_CHIPID2); sc->sc_devrev = (itesio_readreg(sc->sc_iot, sc->sc_ioh, ITESIO_DEVREV) & 0x0f); /* * Select the EC LDN to get the Base Address. */ itesio_writereg(sc->sc_iot, sc->sc_ioh, ITESIO_LDNSEL, ITESIO_EC_LDN); sc->sc_hwmon_baseaddr = (itesio_readreg(sc->sc_iot, sc->sc_ioh, ITESIO_EC_MSB) << 8); sc->sc_hwmon_baseaddr |= itesio_readreg(sc->sc_iot, sc->sc_ioh, ITESIO_EC_LSB); /* * We are done, exit MB PNP mode. */ itesio_exit(sc->sc_iot, sc->sc_ioh); aprint_normal(": iTE IT%4xF Super I/O (rev %d)\n", sc->sc_chipid, sc->sc_devrev); aprint_normal_dev(self, "Hardware Monitor registers at 0x%x\n", sc->sc_hwmon_baseaddr); if (bus_space_map(sc->sc_ec_iot, sc->sc_hwmon_baseaddr, 8, 0, &sc->sc_ec_ioh)) { aprint_error_dev(self, "cannot map hwmon i/o space\n"); goto out2; } sc->sc_hwmon_mapped = true; /* Activate monitoring */ cr = itesio_ecreadreg(sc, ITESIO_EC_CONFIG); SET(cr, 0x01); itesio_ecwritereg(sc, ITESIO_EC_CONFIG, cr); #ifdef notyet /* Enable beep alarms */ cr = itesio_ecreadreg(sc, ITESIO_EC_BEEPEER); SET(cr, 0x02); /* Voltage exceeds limit */ SET(cr, 0x04); /* Temperature exceeds limit */ itesio_ecwritereg(sc, ITESIO_EC_BEEPEER, cr); #endif /* * Initialize and attach sensors. */ itesio_setup_sensors(sc); sc->sc_sme = sysmon_envsys_create(); for (i = 0; i < IT_NUM_SENSORS; i++) { if (sysmon_envsys_sensor_attach(sc->sc_sme, &sc->sc_sensor[i])) { sysmon_envsys_destroy(sc->sc_sme); goto out; } } /* * Hook into the system monitor. */ sc->sc_sme->sme_name = device_xname(self); sc->sc_sme->sme_cookie = sc; sc->sc_sme->sme_refresh = itesio_refresh; if ((i = sysmon_envsys_register(sc->sc_sme))) { aprint_error_dev(self, "unable to register with sysmon (%d)\n", i); sysmon_envsys_destroy(sc->sc_sme); goto out; } sc->sc_hwmon_enabled = true; if (!pmf_device_register(self, NULL, NULL)) aprint_error_dev(self, "couldn't establish power handler\n"); /* The IT8705 doesn't support the WDT */ if (sc->sc_chipid == ITESIO_ID8705) goto out2; /* * Initialize the watchdog timer. */ sc->sc_smw.smw_name = device_xname(self); sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = itesio_wdt_setmode; sc->sc_smw.smw_tickle = itesio_wdt_tickle; sc->sc_smw.smw_period = 60; if (sysmon_wdog_register(&sc->sc_smw)) { aprint_error_dev(self, "unable to register watchdog timer\n"); goto out2; } sc->sc_wdt_enabled = true; aprint_normal_dev(self, "Watchdog Timer present\n"); return; out: bus_space_unmap(sc->sc_ec_iot, sc->sc_ec_ioh, 8); out2: bus_space_unmap(sc->sc_iot, sc->sc_ioh, 2); }
static void acpi_wdrt_attach(device_t parent, device_t self, void *opaque) { struct acpi_wdrt_softc *sc = device_private(self); ACPI_TABLE_WDRT *wdrt; ACPI_STATUS rv; sc->sc_dev = self; pmf_device_register(self, acpi_wdrt_suspend, NULL); rv = AcpiGetTable(ACPI_SIG_WDRT, 1, (ACPI_TABLE_HEADER **)&wdrt); if (ACPI_FAILURE(rv)) { aprint_error(": couldn't get WDRT (%s)\n", AcpiFormatException(rv)); return; } /* Maximum counter value must be 511 - 65535 */ if (wdrt->MaxCount < 511) { aprint_error(": maximum counter value out of range (%d)\n", wdrt->MaxCount); return; } /* Counter units can be 1s, 100ms, or 10ms */ switch (wdrt->Units) { case ACPI_WDRT_UNITS_1S: case ACPI_WDRT_UNITS_100MS: case ACPI_WDRT_UNITS_10MS: break; default: aprint_error(": units not supported (0x%x)\n", wdrt->Units); return; } sc->sc_control_reg = wdrt->ControlRegister; sc->sc_count_reg = wdrt->CountRegister; aprint_naive("\n"); aprint_normal(": mem 0x%" PRIx64 ",0x%" PRIx64 "\n", sc->sc_control_reg.Address, sc->sc_count_reg.Address); if (wdrt->PciVendorId != 0xffff && wdrt->PciDeviceId != 0xffff) { aprint_verbose_dev(sc->sc_dev, "PCI %u:%03u:%02u:%01u", wdrt->PciSegment, wdrt->PciBus, wdrt->PciDevice, wdrt->PciFunction); aprint_verbose(" vendor 0x%04x product 0x%04x\n", wdrt->PciVendorId, wdrt->PciDeviceId); } sc->sc_max_period = wdrt->MaxCount; sc->sc_period_scale = 1; if (wdrt->Units == ACPI_WDRT_UNITS_100MS) sc->sc_period_scale = 10; if (wdrt->Units == ACPI_WDRT_UNITS_10MS) sc->sc_period_scale = 100; sc->sc_max_period /= sc->sc_period_scale; aprint_normal_dev(self, "watchdog interval 1-%d sec.\n", sc->sc_max_period); sc->sc_smw.smw_name = device_xname(self); sc->sc_smw.smw_cookie = sc; sc->sc_smw.smw_setmode = acpi_wdrt_setmode; sc->sc_smw.smw_tickle = acpi_wdrt_tickle; sc->sc_smw.smw_period = sc->sc_max_period; if (sysmon_wdog_register(&sc->sc_smw)) aprint_error_dev(self, "couldn't register with sysmon\n"); else sc->sc_smw_valid = true; }