/*************************************************************************//**
*****************************************************************************/
void HAL_TimerInit(void)
{
halTimerIrqCount = 0;
// System Tick
sysclk_enable_peripheral_clock(SYSTIMER_TICK_CHANNEL_ID);
tc_init(SYSTIMER, SYSTIMER_TICK_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK3 | TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC);
NVIC_DisableIRQ(SYSTIMER_TICK_CHANNEL_IRQn);
NVIC_ClearPendingIRQ(SYSTIMER_TICK_CHANNEL_IRQn);
NVIC_EnableIRQ(SYSTIMER_TICK_CHANNEL_IRQn);
tc_enable_interrupt(SYSTIMER, SYSTIMER_TICK_CHANNEL, TC_IER_CPCS);
tc_write_rc(SYSTIMER, SYSTIMER_TICK_CHANNEL, TIMER_TOP);
tc_start(SYSTIMER, SYSTIMER_TICK_CHANNEL);
sysclk_enable_peripheral_clock(SYSTIMER_DELAY_CHANNEL_ID);
tc_init(SYSTIMER, SYSTIMER_DELAY_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK3 | TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC | TC_CMR_CPCDIS | TC_CMR_CPCSTOP);
NVIC_DisableIRQ(SYSTIMER_DELAY_CHANNEL_IRQn);
NVIC_ClearPendingIRQ(SYSTIMER_DELAY_CHANNEL_IRQn);
NVIC_EnableIRQ(SYSTIMER_DELAY_CHANNEL_IRQn);
tc_enable_interrupt(SYSTIMER, SYSTIMER_DELAY_CHANNEL, TC_IER_CPCS);
}
/*! \brief to enable compare interrupt
*/
void tmr_enable_cc_interrupt(void)
{
tc_get_status(TIMER, TIMER_CHANNEL_ID);
#if SAM4E
tc_enable_interrupt(TIMER, TIMER_CHANNEL_ID, TC_IDR_CPAS);
#else
tc_enable_interrupt(TIMER, TIMER_CHANNEL_ID, TC_IDR_CPCS);
#endif
}
// [main_tc_configure]
static void configure_tc(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Configure PMC */
pmc_enable_periph_clk(ID_TC0);
#if SAMG55
/* Enable PCK output */
pmc_disable_pck(PMC_PCK_3);
pmc_switch_pck_to_sclk(PMC_PCK_3, PMC_PCK_PRES_CLK_1);
pmc_enable_pck(PMC_PCK_3);
#endif
/** Configure TC for a 4Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(4, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 4);
/* Configure and enable interrupt on RC compare */
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
#ifdef LED1_GPIO
/** Start the counter if LED1 is enabled. */
if (g_b_led1_active) {
tc_start(TC0, 0);
}
#else
tc_start(TC0, 0);
#endif
}
/**
* \brief Initialize the timer counter (TC0).
*/
void sys_init_timing(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
/* Clear tick value. */
gs_ul_clk_tick = 0;
/* Configure PMC. */
pmc_enable_periph_clk(ID_TC0);
/* Configure TC for a 1kHz frequency and trigger on RC compare. */
tc_find_mck_divisor(1000,
sysclk_get_main_hz(), &ul_div, &ul_tcclks,
sysclk_get_main_hz());
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (sysclk_get_main_hz() / ul_div) / 1000);
/* Configure and enable interrupt on RC compare. */
NVIC_EnableIRQ((IRQn_Type)ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
/* Start timer. */
tc_start(TC0, 0);
}
void
rtimer_arch_schedule(rtimer_clock_t t)
{
#if DEBUG
printf("DEBUG: rtimer_arch_schedule time %llu\r\n", /*((uint32_t*)&t)+1,*/(uint64_t)t);
#endif
next_rtimer_time = t;
rtimer_clock_t now = rtimer_arch_now();
rtimer_clock_t clock_to_wait = t - now;
if(clock_to_wait <= 0x100000000){ // We must set now the Timer Compare Register.
// Set the auxiliary timer (TC0,1) at the write time interrupt
// [clock_to_wait] TODO Check the standard drift and perhaps remove it from the waiting time
tc_write_rc(TC0,1,(uint32_t)(t-rtimer_arch_now()));
// Set and enable interrupt on RC compare
tc_enable_interrupt(TC0,1,TC_IER_CPCS);
// Start the auxiliary timer
tc_start(TC0,1);
#if DEBUG
now = rtimer_arch_now();
printf("DEBUG: Timer started on time %llu.\n",now);
#endif
}
// else compare register will be set at overflow interrupt closer to the rtimer event.
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
uint32_t cur_time;
uint32_t delta;
cur_time = lp_ticker_read();
delta = timestamp - cur_time;
uint16_t interruptat=0;
if(delta > OVERFLOW_16bit_VALUE) {
lp_ticker_interrupt_counter= (delta/OVERFLOW_16bit_VALUE) -1;
lp_ticker_interrupt_offset=delta%OVERFLOW_16bit_VALUE;
interruptat=OVERFLOW_16bit_VALUE;
} else {
lp_ticker_interrupt_counter=0;
lp_ticker_interrupt_offset=0;
interruptat=delta;
}
NVIC_DisableIRQ(TICKER_COUNTER_IRQn2);
tc_write_rc(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, (uint32_t)interruptat);
NVIC_ClearPendingIRQ(TICKER_COUNTER_IRQn2);
NVIC_SetPriority(TICKER_COUNTER_IRQn2, 0);
NVIC_EnableIRQ(TICKER_COUNTER_IRQn2);
tc_enable_interrupt(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2, TC_IDR_CPCS );
tc_start(TICKER_COUNTER_lp, TICKER_COUNTER_CHANNEL2);
}
void config_uart(void){
/* configura pinos */
gpio_configure_group(PINS_UART0_PIO, PINS_UART0, PINS_UART0_FLAGS);
/* ativa clock */
sysclk_enable_peripheral_clock(CONSOLE_UART_ID);
/* Configuração UART */
const usart_serial_options_t uart_serial_options = {
.baudrate = CONF_UART_BAUDRATE,
.paritytype = UART_MR_PAR_NO,
.stopbits = 0
};
stdio_serial_init((Usart *)CONF_UART, &uart_serial_options);
}
static void configure_tc(void)
{
uint32_t ul_sysclk = sysclk_get_cpu_hz();
pmc_enable_periph_clk(ID_TC0);
tc_init(TC0, 0, TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
tc_write_rc(TC0, 0, 8192);
NVIC_EnableIRQ(ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
tc_start(TC0,0);
}
/**
* Configure Timer Counter 0 to generate an interrupt every 1s.
*/
static void configure_tc(void)
{
/*
* Aqui atualizamos o clock da cpu que foi configurado em sysclk init
*
* O valor atual está em : 120_000_000 Hz (120Mhz)
*/
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/*
* Ativa o clock do periférico TC 0
*/
pmc_enable_periph_clk(ID_TC0);
// Configura TC para operar no modo de comparação e trigger RC
tc_init(TC0,0,TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
// Valor para o contador de um em um segundo.
tc_write_rc(TC0,0,32768);
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
tc_enable_interrupt(TC0,0,TC_IER_CPCS);
tc_start(TC0, 0);
}
void sam_timer_early_init(void)
{
#if 0
pmc_enable_periph_clk(ID_TC0);
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = MCLK; // sysclk_get_cpu_hz();
tc_find_mck_divisor(100, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 4);
tc_find_mck_divisor(100, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, 0xffff); // slowest we can run
/* Configure and enable interrupt on RC compare */
NVIC_SetPriority(ID_TC0, arm_cm_highest_priority());
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
#endif
tc_start(TC0, 0);
arm_cm_systick_init(MCLK);
}
void vInitialiseTimerForIntQueueTest( void )
{
uint32_t ulDivider, ulTCCLKS;
/* Configure PMC for TC0. */
pmc_enable_periph_clk( ID_TC0 );
/* Configure TC0 channel 0 for interrupts at tmrTIMER_0_FREQUENCY. */
tc_find_mck_divisor( tmrTIMER_0_FREQUENCY, configCPU_CLOCK_HZ, &ulDivider, &ulTCCLKS, configCPU_CLOCK_HZ );
tc_init( TC0, 0, ulTCCLKS | TC_CMR_CPCTRG );
ulDivider <<= 1UL;
tc_write_rc( TC0, 0, ( configCPU_CLOCK_HZ / ulDivider ) / tmrTIMER_0_FREQUENCY );
tc_enable_interrupt( TC0, 0, TC_IER_CPCS );
/* Configure and enable interrupts for both TC0 and TC1, as TC1 interrupts
are manually pended from within the TC0 interrupt handler (see the notes at
the top of this file). */
NVIC_ClearPendingIRQ( TC0_IRQn );
NVIC_ClearPendingIRQ( TC1_IRQn );
NVIC_SetPriority( TC0_IRQn, tmrLOWER_PRIORITY );
NVIC_SetPriority( TC1_IRQn, tmrHIGHER_PRIORITY );
NVIC_EnableIRQ( TC0_IRQn );
NVIC_EnableIRQ( TC1_IRQn );
/* Start the timer last of all. */
tc_start( TC0, 0 );
}
// [main_tc_configure]
static void configure_tc(void)
{
uint32_t ul_sysclk = sysclk_get_cpu_hz();
pmc_enable_periph_clk(ID_TC0);
tc_init(TC0,0,TC_CMR_TCCLKS_TIMER_CLOCK5 |TC_CMR_CPCTRG);
tc_write_rc(TC0,0,32000);
tc_enable_interrupt(TC0,0,TC_IER_CPCS);
NVIC_EnableIRQ(ID_TC0);
tc_start(TC0,0);
}
/*! \brief to initialiaze hw timer
*/
uint8_t tmr_init(void)
{
uint8_t tmr_mul;
/* Configure clock service. */
#if SAM4L
sysclk_enable_peripheral_clock(TIMER);
#else
sysclk_enable_peripheral_clock(ID_TC);
#endif
/* Get system clock. */
tmr_mul = sysclk_get_peripheral_bus_hz(TIMER) / DEF_1MHZ;
tmr_mul = tmr_mul >> 1;
#if SAM4L
tc_init(TIMER, TIMER_CHANNEL_ID,
TC_CMR_TCCLKS_TIMER_CLOCK2 | TC_CMR_WAVE |
TC_CMR_WAVSEL_UP_NO_AUTO);
#elif SAM4E
tc_init(TIMER, TIMER_CHANNEL_ID,
TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_WAVE |
TC_CMR_WAVSEL_UP_RC);
#else
tc_init(TIMER, TIMER_CHANNEL_ID,
TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_WAVE |
TC_CMR_WAVSEL_UP);
#endif
/* Configure and enable interrupt on RC compare. */
configure_NVIC(TIMER, TIMER_CHANNEL_ID);
#if SAM4E
tc_get_status(TIMER, TIMER_CHANNEL_ID);
tc_enable_interrupt(TIMER, TIMER_CHANNEL_ID, TC_IER_CPCS);
tc_write_rc(TIMER, TIMER_CHANNEL_ID, UINT16_MAX);
#else
tc_get_status(TIMER, TIMER_CHANNEL_ID);
tc_enable_interrupt(TIMER, TIMER_CHANNEL_ID, TC_IER_COVFS);
#endif
tmr_disable_cc_interrupt();
tc_start(TIMER, TIMER_CHANNEL_ID);
return tmr_mul;
}
void vInitialiseTimerForIntQueueTest( void )
{
uint32_t ulInputFrequency;
/* Calculate the frequency of the clock that feeds the TC. */
ulInputFrequency = configCPU_CLOCK_HZ;
ulInputFrequency /= trmDIVIDER;
/* Three channels are used - two that run at or under
configMAX_SYSCALL_INTERRUPT_PRIORITY, and one that runs over
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
sysclk_enable_peripheral_clock( ID_TC0 );
sysclk_enable_peripheral_clock( ID_TC1 );
sysclk_enable_peripheral_clock( ID_TC2 );
/* Init TC channels to waveform mode - up mode clean on RC match. */
tc_init( TC0, tmrTIMER_0_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG );
tc_init( TC0, tmrTIMER_1_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG );
tc_init( TC0, tmrTIMER_2_CHANNEL, TC_CMR_TCCLKS_TIMER_CLOCK4 | TC_CMR_WAVE | TC_CMR_ACPC_CLEAR | TC_CMR_CPCTRG );
tc_enable_interrupt( TC0, tmrTIMER_0_CHANNEL, tmrTRIGGER_ON_RC );
tc_enable_interrupt( TC0, tmrTIMER_1_CHANNEL, tmrTRIGGER_ON_RC );
tc_enable_interrupt( TC0, tmrTIMER_2_CHANNEL, tmrTRIGGER_ON_RC );
tc_write_rc( TC0, tmrTIMER_0_CHANNEL, ( ulInputFrequency / tmrTIMER_0_FREQUENCY ) );
tc_write_rc( TC0, tmrTIMER_1_CHANNEL, ( ulInputFrequency / tmrTIMER_1_FREQUENCY ) );
tc_write_rc( TC0, tmrTIMER_2_CHANNEL, ( ulInputFrequency / tmrTIMER_2_FREQUENCY ) );
NVIC_SetPriority( TC0_IRQn, tmrTIMER_0_PRIORITY );
NVIC_SetPriority( TC1_IRQn, tmrTIMER_1_PRIORITY );
NVIC_SetPriority( TC2_IRQn, tmrTIMER_2_PRIORITY );
NVIC_EnableIRQ( TC0_IRQn );
NVIC_EnableIRQ( TC1_IRQn );
NVIC_EnableIRQ( TC2_IRQn );
tc_start( TC0, tmrTIMER_0_CHANNEL );
tc_start( TC0, tmrTIMER_1_CHANNEL );
tc_start( TC0, tmrTIMER_2_CHANNEL );
}
/**
* \brief Enable TC1 channel 0 to trigger each second to compute GMAC stats.
*/
static void configure_timer_for_bandwidth_stats(void)
{
pmc_enable_periph_clk(ID_TC3); // Warning TC number is the channel not TC number.
// Hence TC3 means TC1 channel 0.
tc_init(TC1, 0, // Init timer counter 1 channel 0.
TC_CMR_WAVE | // Waveform Mode is enabled.
TC_CMR_CPCTRG | // UP mode with automatic trigger on RC Compare
TC_CMR_TCCLKS_TIMER_CLOCK5 // Use slow clock to avoid overflow.
);
tc_write_rc(TC1, 0, 32768); // Load the highest possible value into TC.
/* Configure TC interrupts for TC TC_CHANNEL_CAPTURE only */
NVIC_SetPriority(TC3_IRQn, 0); // TC3 means TC1 channel 0.
NVIC_EnableIRQ(TC3_IRQn); // TC3 means TC1 channel 0.
tc_enable_interrupt(TC1, 0, TC_IER_CPCS);
tc_start(TC1, 0); // Start Timer counter 0 channel 0.
}
void
rtimer_arch_init(void)
{
/*
* In this implementation we will make use of two Timer Counters (TC).
* The first (TC0) is used to count the universal time, and triggers
* an interrupt on overflow. The timer runs always, and counts the total
* time elapsed since device boot. It is used to extract the current time
* (now)
*
* The second timer (TC1) is used to schedule events in real time.
*/
/* Configure PMC: Enable peripheral clock on component: TC0, channel 0 [see sam3x8e.h] */
pmc_enable_periph_clk(ID_TC0);
/* Configure PMC: Enable peripheral clock on component: TC0, channel 1 [see sam3x8e.h] */
pmc_enable_periph_clk(ID_TC1);
/* Configure the TC0 for 10500000 Hz and trigger on RC register compare */
tc_init(TC0, 0, RT_PRESCALER | TC_CMR_CPCTRG);
/* Configure the TC1 for 10500000 Hz and trigger on RC register compare */
tc_init(TC0, 1, RT_PRESCALER | TC_CMR_CPCTRG);
/* Disable all interrupts on both counters*/
tc_disable_interrupt(TC0,0,0b11111111);
tc_disable_interrupt(TC0,1,0b11111111);
/* Configure the main counter to trigger an interrupt on RC compare (overflow) */
tc_write_rc(TC0, 0, 0xffffffff);
/* Configure interrupt on the selected timer channel, setting the corresponding callback */
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
/* Configure interrupt on the selected timer channel, setting the corresponding callback */
NVIC_EnableIRQ((IRQn_Type) ID_TC1);
/* Enable TC0 interrupt on RC Compare */
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
/* Start the universal time counter */
tc_start(TC0, 0);
#if DEBUG
printf("DEBUG: Universal Real-Timer started.\n");
#endif
}
static void setup_capture(void)
{
ioport_set_pin_mode(PIN_TC0_TIOA0, PIN_TC0_TIOA0_MUX);
ioport_disable_pin(PIN_TC0_TIOA0);
ioport_set_pin_mode(PIN_TC0_TIOA1, PIN_TC0_TIOA1_MUX);
ioport_disable_pin(PIN_TC0_TIOA1);
ioport_set_pin_mode(PIN_TC0_TIOB2, PIN_TC0_TIOB2_MUX);
ioport_disable_pin(PIN_TC0_TIOB2);
configure_tc_capture();
NVIC_DisableIRQ((IRQn_Type) ID_TC0);
NVIC_ClearPendingIRQ((IRQn_Type) ID_TC0);
NVIC_SetPriority((IRQn_Type) ID_TC0, 0);
NVIC_EnableIRQ((IRQn_Type) ID_TC0);
//tc_enable_interrupt(TC0, 0, TC_IER_ETRGS);
tc_enable_interrupt(TC0, 0, TC_IER_LDRAS);
tc_enable_interrupt(TC0, 0, TC_IER_LDRBS);
NVIC_DisableIRQ((IRQn_Type) ID_TC1);
NVIC_ClearPendingIRQ((IRQn_Type) ID_TC1);
NVIC_SetPriority((IRQn_Type) ID_TC1, 0);
NVIC_EnableIRQ((IRQn_Type) ID_TC1);
//tc_enable_interrupt(TC0, 1, TC_IER_ETRGS);
tc_enable_interrupt(TC0, 1, TC_IER_LDRAS);
tc_enable_interrupt(TC0, 1, TC_IER_LDRBS);
NVIC_DisableIRQ((IRQn_Type) ID_TC2);
NVIC_ClearPendingIRQ((IRQn_Type) ID_TC2);
NVIC_SetPriority((IRQn_Type) ID_TC2, 0);
NVIC_EnableIRQ((IRQn_Type) ID_TC2);
tc_enable_interrupt(TC0, 2, TC_IER_ETRGS);
tc_enable_interrupt(TC0, 2, TC_IER_LDRAS);
tc_enable_interrupt(TC0, 2, TC_IER_LDRBS);
tc_start(TC0, 0);
tc_start(TC0, 1);
tc_start(TC0, 2);
}
/**
* \brief Configure Timer Counter 0 (TC0) to generate an interrupt every 200ms.
* This interrupt will be used to flush USART input and echo back.
*/
static void configure_tc(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
static uint32_t ul_sysclk;
/* Get system clock. */
ul_sysclk = sysclk_get_cpu_hz();
/* Configure PMC. */
pmc_enable_periph_clk(ID_TC0);
/* Configure TC for a 50Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(TC_FREQ, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / TC_FREQ);
/* Configure and enable interrupt on RC compare. */
NVIC_EnableIRQ((IRQn_Type)ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
}
/**
* \brief Configure Timer Counter 0 (TC0) to generate an interrupt every 200ms.
* This interrupt will be used to flush USART input and echo back.
*/
static void configure_tc(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
static uint32_t ul_pbaclk;
/* Configure clock service. */
sysclk_enable_peripheral_clock(TC0);
/* Get system clock. */
ul_pbaclk = sysclk_get_peripheral_bus_hz(TC0);
/* Configure TC for a 1Hz frequency and trigger on RC compare. */
tc_find_mck_divisor(TC_FREQ, ul_pbaclk, &ul_div, &ul_tcclks, ul_pbaclk);
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_pbaclk / ul_div) / TC_FREQ);
/* Configure and enable interrupt on RC compare. */
NVIC_EnableIRQ(TC00_IRQn);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
}
void TC0_Handler(void)
{
volatile uint32_t ul_dummy, TC_value;
/* Get the current timer counter value from a 32-bit register*/
TC_value = tc_read_tc(TC0,0);
/* Clear status bit to acknowledge interrupt */
ul_dummy = tc_get_status(TC0, 0);
if ((ul_dummy & TC_SR_CPCS) == TC_SR_CPCS) {
#if DEBUG
printf("%08x OV \n",TC_value);
#endif
time_msb++;
rtimer_clock_t now = ((rtimer_clock_t)time_msb << 32)|tc_read_tc(TC0,0);
rtimer_clock_t clock_to_wait = next_rtimer_time - now;
if(clock_to_wait <= 0x100000000 && clock_to_wait > 0)
{
// We must set now the Timer Compare Register.
// Set the auxiliary timer (TC0,1) at the write time interrupt
tc_write_rc(TC0,1,(uint32_t)clock_to_wait);
// Set and enable interrupt on RC compare
tc_enable_interrupt(TC0,1,TC_IER_CPCS);
// Start the auxiliary timer
tc_start(TC0,1);
}
}
else {
printf("ERROR: TC: Unknown interrupt.\n");
}
}
/**
* \brief Configure Timer Counter 0 to generate an interrupt with the specific
* frequency.
*
* \param freq Timer counter frequency.
*/
static void configure_tc(uint32_t freq)
{
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Disable TC first */
tc_stop(TC0, 0);
tc_disable_interrupt(TC0, 0, TC_IER_CPCS);
/** Configure TC with the frequency and trigger on RC compare. */
tc_find_mck_divisor(freq, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 4);
/* Configure and enable interrupt on RC compare */
NVIC_EnableIRQ((IRQn_Type)ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
/** Start the counter. */
tc_start(TC0, 0);
}
static void configure_tc(void)
{
/*
* Aqui atualizamos o clock da cpu que foi configurado em sysclk init
*
* O valor atual est'a em : 120_000_000 Hz (120Mhz)
*/
uint32_t ul_sysclk = TC_CMR_TCCLKS_TIMER_CLOCK5;
/*
* Ativa o clock do periférico TC 0
*
*/
pmc_enable_periph_clk(ID_TC0);
/*
* Configura TC para operar no modo de comparação e trigger RC
* devemos nos preocupar com o clock em que o TC irá operar !
*
* Cada TC possui 3 canais, escolher um para utilizar.
*
* Uma opção para achar o valor do divisor é utilizar a funcao
* tc_find_mck_divisor()
*/
tc_init(TC0, 0, TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
tc_write_rc(TC0, 0, 534);
/*
* Devemos configurar o NVIC para receber interrupções do TC
*/
NVIC_EnableIRQ(ID_TC0);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
tc_start(TC0,0);
}
void setup_timeoutcnt(void)
{
sysclk_enable_peripheral_clock(ID_TC0);
/* Configure TC interrupts for TC TC_CHANNEL_CAPTURE only */
irq_register_handler(TC0_IRQn, 1);
// Init TC to waveform mode.
tc_init(TC0, TC_CHANNEL_TICKCNT,
1 /* Clock = 96MHz / 8 */
| TC_CMR_WAVE // Waveform mode is enabled
| TC_CMR_CPCTRG
);
// Configure waveform frequency and duty cycle.
uint32_t rc = (sysclk_get_peripheral_bus_hz(TC0) /
TC_WAVEFORM_DIVISOR /
TC_WAVEFORM_FREQUENCY);
tc_write_rc(TC0, TC_CHANNEL_TICKCNT, rc);
tc_enable_interrupt(TC0, TC_CHANNEL_TICKCNT, TC_IER_CPCS);
timerEnabled = true;
}
/** @brief Init Timer interrupt (1ms)
*
* Initialize 1mSec timer 3 interrupt */
void initTimer1ms(void)
{
uint32_t ul_div, ul_tcclks;
/* Configure PMC */
pmc_enable_periph_clk(ID_TC_1MS);
/* MCK = 120000000 -> tcclks = 2 : TCLK3 = MCK/32 = 3750000 = 0.266us ->
* ul_div = 1ms/0.2666us = 3750 */
ul_tcclks = 2;
ul_div = 3750;
tc_init(TC_1MS, TC_1MS_CHN, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC_1MS, TC_1MS_CHN, ul_div);
/* Configure and enable interrupt on RC compare */
NVIC_SetPriority((IRQn_Type)ID_TC_1MS, 0);
NVIC_EnableIRQ((IRQn_Type)ID_TC_1MS);
tc_enable_interrupt(TC_1MS, TC_1MS_CHN, TC_IER_CPCS);
/** Start the timer. TC1, chanel 0 = TC3 */
tc_start(TC_1MS, TC_1MS_CHN);
}
/**
* Configure Timer Counter 0 to generate an interrupt every 200ms.
*/
static void configure_tc(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Configure TC0 */
sysclk_enable_peripheral_clock(TC0);
/* Configure TC for a 5Hz frequency and trigger on RC compare. */
if (!tc_find_mck_divisor(5, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk)) {
puts("No valid divisor found!\r");
return;
}
tc_init(TC0, 0, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 0, (ul_sysclk / ul_div) / 5);
/* Configure and enable interrupt on RC compare */
NVIC_EnableIRQ((IRQn_Type) TC00_IRQn);
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
/* Start the counter. */
tc_start(TC0, 0);
}
/**
* \brief Configure Timer Counter to generate an interrupt every 10ms.
* This interrupt will be used to flush UART input and echo back.
*/
static void _configure_TC_uart(void)
{
uint32_t ul_div;
uint32_t ul_tcclks;
uint32_t ul_sysclk;
uint32_t ul_frec_hz = (uint32_t)FREQ_TIMER_POLL_UART;
/* Get system clock. */
ul_sysclk = sysclk_get_cpu_hz();
/* Configure PMC. */
pmc_enable_periph_clk(ID_TC_UART);
/* Configure TC for a TC_FREQ frequency and trigger on RC compare. */
tc_find_mck_divisor(ul_frec_hz, ul_sysclk, &ul_div, &ul_tcclks,
ul_sysclk);
tc_init(TC_UART, TC_UART_CHN, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC_UART, TC_UART_CHN, (ul_sysclk / ul_div) / ul_frec_hz);
/* Configure and enable interrupt on RC compare. */
NVIC_SetPriority((IRQn_Type)ID_TC_UART, TIMER_UART_PRIO);
NVIC_EnableIRQ((IRQn_Type)ID_TC_UART);
tc_enable_interrupt(TC_UART, TC_UART_CHN, TC_IER_CPCS);
}
void config_tccapture_freq(void){
/** Configure PIO Pins for TC */
ioport_set_pin_mode(PIN_TC0_TIOA2, PIN_TC0_TIOA2_MUX );
/** Disable I/O to enable peripheral mode) */
ioport_disable_pin(PIN_TC0_TIOA2);
sysclk_enable_peripheral_clock(ID_TC2);
tc_init(TC0, TC_CHANNEL_CAP_FREQ,
TC_CAPTURE_TCCLKS | // Clock Selection = MCLK/32 CLK3
TC_CMR_LDRA_RISING | // RA Loading = Rising edge of TIOA
TC_CMR_LDRB_FALLING | // RB Loading = Falling Edge of TIOA
TC_CMR_ABETRG | // External Trigger = TIOA
TC_CMR_ETRGEDG_FALLING // External Trigger Edge = Falling Edge
);
NVIC_DisableIRQ(TC2_IRQn);
NVIC_ClearPendingIRQ(TC2_IRQn);
NVIC_SetPriority(TC2_IRQn, PRIORITY_MEASURE);
NVIC_EnableIRQ(TC2_IRQn);
tc_enable_interrupt(TC0, TC_CHANNEL_CAP_FREQ, TC_IER_LDRBS);
tc_start(TC0, TC_CHANNEL_CAP_FREQ);
}
void config_tccapture_duty(void){
/** Configure PIO Pins for TC */
ioport_set_pin_mode(PIO_PC23_IDX, IOPORT_MODE_MUX_B );
/** Disable I/O to enable peripheral mode) */
ioport_disable_pin(PIO_PC23_IDX);
sysclk_enable_peripheral_clock(ID_TC3);
tc_init(TC1, TC_CHANNEL_CAP_DUTY,
TC_CAP_DUTY_TCCLKS | // Clock Selection = MCLK/32
TC_CMR_LDRA_RISING | // RA Loading = Rising edge of TIOA
TC_CMR_LDRB_FALLING | // RB Loading = Falling Edge of TIOA
TC_CMR_ABETRG | // External Trigger = TIOA
TC_CMR_ETRGEDG_FALLING // External Trigger Edge = Falling Edge
);
NVIC_DisableIRQ(TC3_IRQn);
NVIC_ClearPendingIRQ(TC3_IRQn);
NVIC_SetPriority(TC3_IRQn, PRIORITY_MEASURE);
NVIC_EnableIRQ(TC3_IRQn);
tc_enable_interrupt(TC1, TC_CHANNEL_CAP_DUTY, TC_IER_LDRBS);
tc_start(TC1, TC_CHANNEL_CAP_DUTY);
}
static void configure_tc(void)
{
/****************************************************************
* Devemos indicar ao TC que a interrupção foi satisfeita.
******************************************************************/
// [main_tc_configure]
/*
* Aqui atualizamos o clock da cpu que foi configurado em sysclk init
*
* O valor atual est'a em : 120_000_000 Hz (120Mhz)
*/
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/****************************************************************
* Ativa o clock do periférico TC 0
*****************************************************************
*
* Parametros :
* 1 - ID do periferico
*
*
*****************************************************************/
pmc_enable_periph_clk(ID_TC0);
/*****************************************************************
* Configura TC para operar no modo de comparação e trigger RC
*****************************************************************
*
* Configura TC para operar no modo de comparação e trigger RC
* devemos nos preocupar com o clock em que o TC irá operar !
*
* Cada TC possui 3 canais, escolher um para utilizar.
*
* No nosso caso :
*
* MCK = 120_000_000
* SLCK = 32_768 (rtc)
*
* Uma opção para achar o valor do divisor é utilizar a funcao, como ela
* funciona ?
* tc_find_mck_divisor()
*
*
* Parametros
* 1 - TC a ser configurado (TC0,TC1, ...)
* 2 - Canal a ser configurado (0,1,2)
* 3 - Configurações do TC :
*
*
* Configurações de modo de operação :
* TC_CMR_ABETRG : TIOA or TIOB External Trigger Selection
* TC_CMR_CPCTRG : RC Compare Trigger Enable
* TC_CMR_WAVE : Waveform Mode
*
* Configurações de clock :
* TC_CMR_TCCLKS_TIMER_CLOCK1 : Clock selected: internal MCK/2 clock signal
* TC_CMR_TCCLKS_TIMER_CLOCK2 : Clock selected: internal MCK/8 clock signal
* TC_CMR_TCCLKS_TIMER_CLOCK3 : Clock selected: internal MCK/32 clock signal
* TC_CMR_TCCLKS_TIMER_CLOCK4 : Clock selected: internal MCK/128 clock signal
* TC_CMR_TCCLKS_TIMER_CLOCK5 : Clock selected: internal SLCK clock signal
*
*****************************************************************/
tc_init(TC0, 0, TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
/*****************************************************************
* Configura valor trigger RC
*****************************************************************
*
* Aqui devemos configurar o valor do RC que vai trigar o reinicio da contagem
* devemos levar em conta a frequência que queremos que o TC gere as interrupções
* e tambem a frequencia com que o TC está operando.
*
* Devemos configurar o RC para o mesmo canal escolhido anteriormente.
*
* ^
* | Contador (incrementado na frequencia escolhida do clock)
* |
* | Interrupcao
* |------#----------- RC
* | /
* | /
* | /
* |-----------------> t
*
* Parametros :
* 1 - TC a ser configurado (TC0,TC1, ...)
* 2 - Canal a ser configurado (0,1,2)
* 3 - Valor para trigger do contador (RC)
*****************************************************************/
tc_write_rc(TC0,0,32768);
/*****************************************************************
* Configura interrupção no TC
*****************************************************************
* Parametros :
* 1 - TC a ser configurado
* 2 - Canal
* 3 - Configurações das interrupções
*
* Essas configurações estão definidas no head : tc.h
*
* TC_IER_COVFS : Counter Overflow
* TC_IER_LOVRS : Load Overrun
* TC_IER_CPAS : RA Compare
* TC_IER_CPBS : RB Compare
* TC_IER_CPCS : RC Compare
* TC_IER_LDRAS : RA Loading
* TC_IER_LDRBS : RB Loading
* TC_IER_ETRGS : External Trigger
*****************************************************************/
tc_enable_interrupt(TC0,0,TC_IER_CPCS);
/*****************************************************************
* Ativar interrupção no NVIC*/
NVIC_EnableIRQ(ID_TC0);
/*****************************************************************
* Inicializa o timer
*****************************************************************
*
* Parametros :
* 1 - TC
* 2 - Canal
*****************************************************************/
tc_start(TC0,0);
/************************************************************************/
/* Main Code
*/
/************************************************************************/
// Here should be all the initialization functions for the module before 12v power
void init_module_peripherals_bp(void)
{
/* LEDs IO */
pmc_enable_periph_clk(IN_CLK_LED1_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_CLK_LED2_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_CLK_LED3_PIO_ID);
ioport_set_pin_dir(IN_CLK_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_CLK_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED1_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED2_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(IN_DAT_LED3_PIO_ID);
ioport_set_pin_dir(IN_DAT_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(IN_DAT_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED1_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED2_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH1_CH2_LED3_PIO_ID);
ioport_set_pin_dir(OUT_CH1_CH2_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH1_CH2_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED1_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED1_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED2_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED2_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
pmc_enable_periph_clk(OUT_CH3_LED3_PIO_ID);
ioport_set_pin_dir(OUT_CH3_LED3_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_CH3_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
/* Pulse inputs/state & d reset output */
pmc_enable_periph_clk(OUT_PULSE_DET_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(DATA_IN_DET_PIO_ID);
ioport_set_pin_dir(DATA_IN_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(CLK_IN_DET_PIO_ID);
ioport_set_pin_dir(CLK_IN_DET_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(OUT_PULSE_STATE_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(DATA_IN_STATE_PIO_ID);
ioport_set_pin_dir(DATA_IN_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(CLK_IN_STATE_PIO_ID);
ioport_set_pin_dir(CLK_IN_STATE_GPIO, IOPORT_DIR_INPUT);
pmc_enable_periph_clk(OUT_PULSE_RST_PIO_ID);
ioport_set_pin_dir(OUT_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(OUT_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(DATA_PULSE_RST_PIO_ID);
ioport_set_pin_dir(DATA_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(CLK_PULSE_RST_PIO_ID);
ioport_set_pin_dir(CLK_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLK_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
/* Sload */
pmc_enable_periph_clk(DATA_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(DATA_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(CLOCK_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(CLOCK_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLOCK_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(RESET_DELAY_SLOAD_PIO_ID);
ioport_set_pin_dir(RESET_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RESET_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
pmc_enable_periph_clk(RF_ATTEN_SLOAD_PIO_ID);
ioport_set_pin_dir(RF_ATTEN_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RF_ATTEN_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
/* Delay enables */
pmc_enable_periph_clk(DATA_DELAY_EN_PIO_ID);
ioport_set_pin_dir(DATA_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(DATA_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
pmc_enable_periph_clk(CLOCK_DELAY_EN_PIO_ID);
ioport_set_pin_dir(CLOCK_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(CLOCK_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
pmc_enable_periph_clk(RESET_DELAY_EN_PIO_ID);
ioport_set_pin_dir(RESET_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
ioport_set_pin_level(RESET_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH); // default state is HIGH (OG 10.04.2014)
// Init LED interrupt,
uint32_t ul_div;
uint32_t ul_tcclks;
/* Get system clock. */
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/* Configure PMC. */
pmc_enable_periph_clk(ID_TC1);
/* Configure TC for a TC_FREQ frequency and trigger on RC compare. */
tc_find_mck_divisor(20, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
tc_init(TC0, 1, ul_tcclks | TC_CMR_CPCTRG);
tc_write_rc(TC0, 1, (ul_sysclk / ul_div) / 20);
/* Configure and enable interrupt on RC compare. */
tc_start(TC0, 1);
NVIC_DisableIRQ(TC1_IRQn);
NVIC_ClearPendingIRQ(TC1_IRQn);
//NVIC_SetPriority(TC1_IRQn, 0);
NVIC_EnableIRQ((IRQn_Type)ID_TC1);
tc_enable_interrupt(TC0, 1, TC_IER_CPCS);
/* SPI interface */
gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS);
gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS);
gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS);
//gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); // Controled by software
/* Configure an SPI peripheral. */
spi_enable_clock(SPI0);
spi_disable(SPI0);
spi_reset(SPI0);
spi_set_lastxfer(SPI0);
spi_set_master_mode(SPI0);
spi_disable_mode_fault_detect(SPI0);
/* Set variable chip select */
spi_set_variable_peripheral_select(SPI0);
/* Configure delay SPI channel */
spi_set_clock_polarity(SPI0, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI0, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI0, SPI_CHIP_SEL, SPI_CSR_BITS_11_BIT);
spi_configure_cs_behavior(SPI0, SPI_CHIP_SEL, SPI_CS_RISE_FORCED);
spi_set_baudrate_div(SPI0, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI0, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
/* Configure RF atten SPI channel */
spi_set_clock_polarity(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI0, SPI_ALT_CHIP_SEL, SPI_CSR_BITS_16_BIT);
spi_configure_cs_behavior(SPI0, SPI_ALT_CHIP_SEL, SPI_CS_RISE_FORCED);
spi_set_baudrate_div(SPI0, SPI_ALT_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
spi_set_transfer_delay(SPI0, SPI_ALT_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
/* Enable SPI */
spi_enable(SPI0);
}
// [main_tc_configure]
static void configure_tc(void)
{
/*
* Aqui atualizamos o clock da cpu que foi configurado em sysclk init
*
* O valor atual est'a em : 120_000_000 Hz (120Mhz)
*/
uint32_t ul_sysclk = sysclk_get_cpu_hz();
/*
* Ativa o clock do periférico TC 0
*
*/
pmc_enable_periph_clk(ID_TC0);
/*
* Configura TC para operar no modo de comparação e trigger RC
* devemos nos preocupar com o clock em que o TC irá operar !
*
* Cada TC possui 3 canais, escolher um para utilizar.
*
* Configurações de modo de operação :
* #define TC_CMR_ABETRG (0x1u << 10) : TIOA or TIOB External Trigger Selection
* #define TC_CMR_CPCTRG (0x1u << 14) : RC Compare Trigger Enable
* #define TC_CMR_WAVE (0x1u << 15) : Waveform Mode
*
* Configurações de clock :
* #define TC_CMR_TCCLKS_TIMER_CLOCK1 : Clock selected: internal MCK/2 clock signal
* #define TC_CMR_TCCLKS_TIMER_CLOCK2 : Clock selected: internal MCK/8 clock signal
* #define TC_CMR_TCCLKS_TIMER_CLOCK3 : Clock selected: internal MCK/32 clock signal
* #define TC_CMR_TCCLKS_TIMER_CLOCK4 : Clock selected: internal MCK/128 clock signal
* #define TC_CMR_TCCLKS_TIMER_CLOCK5 : Clock selected: internal SLCK clock signal
*
* MCK = 120_000_000
* SLCK = 32_768 (rtc)
*
* Uma opção para achar o valor do divisor é utilizar a funcao
* tc_find_mck_divisor()
*/
tc_init(TC0, 0, TC_CMR_CPCTRG | TC_CMR_TCCLKS_TIMER_CLOCK5);
/*
* Aqui devemos configurar o valor do RC que vai trigar o reinicio da contagem
* devemos levar em conta a frequência que queremos que o TC gere as interrupções
* e tambem a frequencia com que o TC está operando.
*
* Devemos configurar o RC para o mesmo canal escolhido anteriormente.
*
* ^
* | Contador (incrementado na frequencia escolhida do clock)
* |
* | Interrupcao
* |------#----------- RC
* | /
* | /
* | /
* |-----------------> t
*
*
*/
tc_write_rc(TC0, 0, 8192);
/*
* Devemos configurar o NVIC para receber interrupções do TC
*/
NVIC_EnableIRQ(ID_TC0);
/*
* Opções possíveis geradoras de interrupção :
*
* Essas configurações estão definidas no head : tc.h
*
* #define TC_IER_COVFS (0x1u << 0) Counter Overflow
* #define TC_IER_LOVRS (0x1u << 1) Load Overrun
* #define TC_IER_CPAS (0x1u << 2) RA Compare
* #define TC_IER_CPBS (0x1u << 3) RB Compare
* #define TC_IER_CPCS (0x1u << 4) RC Compare
* #define TC_IER_LDRAS (0x1u << 5) RA Loading
* #define TC_IER_LDRBS (0x1u << 6) RB Loading
* #define TC_IER_ETRGS (0x1u << 7) External Trigger
*/
tc_enable_interrupt(TC0, 0, TC_IER_CPCS);
tc_start(TC0,0);
}
